improve RX timings (make valid synchronous)

liteeth/common.py

@@ -7,8 +7,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.record import *
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import chooser
-from migen.flow.actor import EndpointDescription
-from migen.flow.actor import Sink, Source
+from migen.flow.actor import *
+from migen.flow.plumbing import Buffer
 from migen.actorlib.structuring import Converter, Pipeline
 from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
 from migen.bank.description import *

liteeth/core/arp/__init__.py

@@ -96,7 +96,7 @@ class LiteEthARPRX(Module):
 			)
 		)
 		valid = Signal()
-		self.comb += valid.eq(
+		self.sync += valid.eq(
 			depacketizer.source.stb &
 			(depacketizer.source.hwtype == arp_hwtype_ethernet) &
 			(depacketizer.source.proto == arp_proto_ip) &

liteeth/core/icmp/__init__.py

@@ -71,7 +71,7 @@ class LiteEthICMPRX(Module):
 			)
 		)
 		valid = Signal()
-		self.comb += valid.eq(
+		self.sync += valid.eq(
 			depacketizer.source.stb &
 			(sink.protocol == icmp_protocol)
 		)

liteeth/core/ip/__init__.py

@@ -136,7 +136,7 @@ class LiteEthIPRX(Module):
 			)
 		)
 		valid = Signal()
-		self.comb += valid.eq(
+		self.sync += valid.eq(
 			depacketizer.source.stb &
 			(depacketizer.source.target_ip == ip_address) &
 			(depacketizer.source.version == 0x4) &

liteeth/core/udp/__init__.py

@@ -72,7 +72,7 @@ class LiteEthUDPRX(Module):
 			)
 		)
 		valid = Signal()
-		self.comb += valid.eq(
+		self.sync += valid.eq(
 			depacketizer.source.stb &
 			(sink.protocol == udp_protocol)
 		)