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soc: use new ModuleTransformer API

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Sebastien Bourdeauducq 2015-04-06 23:52:34 +08:00
parent 66f8dcbfaf
commit 176b9240a9
1 changed files with 1 additions and 1 deletions
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2
misoclib/soc/sdram.py
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@ -61,7 +61,7 @@ class SDRAMSoC(SoC):
from mibuild.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
self.submodules.wishbone2lasmi = FullMemoryWE()(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
else:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())
self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)