efinix: RGMII phy should be operational (no tested)
PLL infrastructure should be complete now. We can also use DDIO input and outputs. However, there is problem (bug) during P&R: ERROR(1): [Line 52] Block auto_eth_tx_delayed_clk is an output pad but sub-block 1 is not an output pad location. Inderface Designer validation doesn't report any problem. I have a test project with the same configuration (I compared the reports for blocks configuration) and it works.
This commit is contained in:
Franck Jullien
parent
109dbd1d62
commit
179a8018b3
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@ -180,15 +180,70 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
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return b
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return None
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def generate_gpio(self, block, verbose=True):
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name = block['name']
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mode = block['mode']
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cmd = ''
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# TODO: {'type': 'GPIO', 'mode': 'OUTPUT', 'location': 'U16', 'size': 4, 'in_reg': 'DDIO_RESYNC', 'out_clk_pin': '', 'is_inclk_inverted': False, 'name': 'auto_ethtx_tx_data_d1', 'name_d2': 'auto_ethtx_tx_data_d2'}
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if mode == 'INPUT':
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if len(block['location']) == 1:
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cmd += 'design.create_input_gpio("{}")\n'.format(name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n'.format(name, block['location'][0])
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else:
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cmd += 'design.create_input_gpio("{}",{},0)\n'.format(name, block['size']-1)
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for i, pad in enumerate(block['location']):
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cmd += 'design.assign_pkg_pin("{}[{}]","{}")\n'.format(name, i, pad)
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if 'in_reg' in block:
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cmd += 'design.set_property("{}","IN_REG","{}")\n'.format(name, block['in_reg'])
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cmd += 'design.set_property("{}","IN_CLK_PIN","{}")\n\n'.format(name, block['in_clk_pin'])
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return cmd
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if mode == 'OUTPUT':
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if len(block['location']) == 1:
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cmd += 'design.create_output_gpio("{}")\n'.format(name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n'.format(name, block['location'][0])
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else:
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cmd += 'design.create_input_gpio("{}",{},0)\n'.format(name, block['size']-1)
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for i, pad in enumerate(block['location']):
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cmd += 'design.assign_pkg_pin("{}[{}]","{}")\n'.format(name, i, pad)
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if 'out_reg' in block:
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cmd += 'design.set_property("{}","OUT_REG","{}")\n'.format(name, block['out_reg'])
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cmd += 'design.set_property("{}","OUT_CLK_PIN","{}")\n\n'.format(name, block['out_clk_pin'])
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return cmd
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if mode == 'INPUT_CLK':
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cmd += 'design.create_input_clock_gpio("{}")\n'.format(name)
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cmd += 'design.set_property("{}","IN_PIN","{}")\n'.format(name, name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block['location'])
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return cmd
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if mode == 'OUTPUT_CLK':
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cmd += 'design.create_clockout_gpio("{}")\n'.format(name)
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cmd += 'design.set_property("{}","OUT_CLK_PIN","{}")\n'.format(name, name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block['location'])
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return cmd
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cmd = '# TODO: ' + str(block) +'\n'
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return cmd
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def generate_pll(self, block, verbose=True):
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name = block['name']
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cmd = '# ---------- PLL {} ---------\n'.format(name)
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cmd += 'design.create_block("{}", block_type="PLL")\n'.format(name)
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
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.format(name, block['resource'], block['input_clock'], block['input_clock_name'], block['clock_no'])
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cmd += 'pll_config = {{ "REFCLK_FREQ":"{}" }}\n'.format(block['input_freq'] / 1e6)
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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if block['input_clock'] == 'EXTERNAL':
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
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.format(name, block['resource'], block['input_clock'], block['input_clock_name'], block['clock_no'])
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else:
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_name="{}", refclk_src="CORE")\n'.format(name, block['resource'], block['input_signal'])
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cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block['input_signal'])
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cmd += 'pll_config = {{ "REFCLK_FREQ":"{}" }}\n'.format(block['input_freq'] / 1e6)
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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cmd += 'design.set_property("{}","LOCKED_PIN","{}", block_type="PLL")\n'.format(name, block['locked'])
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if block['reset'] != '':
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@ -198,10 +253,10 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
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for i, clock in enumerate(block['clk_out']):
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if i > 0:
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cmd += 'pll_config = {{ "CLKOUT{}_EN":"1", "CLKOUT{}_PIN":"{}" }}\n'.format(i, i, clock[0])
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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else:
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cmd += 'pll_config = {{ "CLKOUT{}_PIN":"{}" }}\n'.format(i, clock[0])
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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cmd += 'target_freq = {\n'
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for i, clock in enumerate(block['clk_out']):
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@ -215,8 +270,8 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
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cmd += 'print("#### {} ####")\n'.format(name)
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cmd += 'clksrc_info = design.trace_ref_clock("{}", block_type="PLL")\n'.format(name)
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cmd += 'pprint.pprint(clksrc_info)\n'
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cmd += 'clock_source_prop = ["REFCLK_SOURCE", "EXT_CLK", "CLKOUT0_EN", "CLKOUT1_EN","REFCLK_FREQ", "RESOURCE"]\n'
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cmd += 'clock_source_prop += ["M", "N", "O", "CLKOUT0_DIV", "CLKOUT2_DIV", "VCO_FREQ", "PLL_FREQ"]\n'
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cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "CLKOUT0_EN", "CLKOUT1_EN","REFCLK_FREQ", "RESOURCE"]\n'
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cmd += 'clock_source_prop += ["CLKOUT0_FREQ", "CLKOUT1_FREQ", "CLKOUT2_FREQ"]\n'
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cmd += 'prop_map = design.get_property("{}", clock_source_prop, block_type="PLL")\n'.format(name)
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cmd += 'pprint.pprint(prop_map)\n'
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@ -228,6 +283,9 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
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for b in self.blocks:
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if b['type'] == 'PLL':
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output += self.generate_pll(b)
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if b['type'] == 'GPIO':
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output += self.generate_gpio(b)
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return output
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def footer(self):
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@ -18,6 +18,9 @@ class EfinixPlatform(GenericPlatform):
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def __init__(self, *args, toolchain="efinity", **kwargs):
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GenericPlatform.__init__(self, *args, **kwargs)
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self.pll_available = ['PLL_TL0', 'PLL_TR0', 'PLL_TR1', 'PLL_TR2', 'PLL_TR3', 'PLL_BR0', 'PLL_BR1', 'PLL_BR2', 'PLL_BL0']
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self.pll_used = []
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if 'LITEX_ENV_EFINITY' in os.environ:
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self.efinity_path = os.environ['LITEX_ENV_EFINITY'].rstrip('/')
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os.environ['EFINITY_HOME'] = self.efinity_path
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@ -55,29 +58,63 @@ class EfinixPlatform(GenericPlatform):
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# get_pin_location(p[1])
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# not tested with subsignal like get_pin_location(p.clk)
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def get_pin_location(self, sig):
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if sig is None:
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return None
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sc = self.constraint_manager.get_sig_constraints()
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for s, pins, others, resource in sc:
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if s == sig:
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return pins[0]
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if (s == sig) and (pins[0] != 'X'):
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return pins
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return None
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def get_pin_name(self, sig):
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if sig is None:
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return None
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sc = self.constraint_manager.get_sig_constraints()
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for s, pins, others, resource in sc:
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if s == sig:
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return resource[0]
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if resource[2]:
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return resource[0] + '_' + resource[2]
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else:
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return resource[0]
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return None
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def add_iface_io(self, name, size=1):
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def get_sig_constraint(self, sig):
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sc = self.constraint_manager.get_sig_constraints()
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for s, pins, others, resource in sc:
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if s == sig:
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return sc
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return None
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def add_iface_io(self, name, size=1, append=True):
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self.add_extension([(name, 0, Pins(size))])
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tmp = self.request(name)
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# We don't want this IO to be in the interface configuration file as a simple GPIO
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self.toolchain.specials_gpios.append(tmp)
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if append:
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self.toolchain.specials_gpios.append(tmp)
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return tmp
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def add_iface_ios(self, io):
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def add_iface_ios(self, io, append=True):
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self.add_extension(io)
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tmp = self.request(io[0][0])
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for s in tmp.flatten():
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self.toolchain.specials_gpios.append(s)
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if append:
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for s in tmp.flatten():
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self.toolchain.specials_gpios.append(s)
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return tmp
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def del_record_signal(self, record, sig):
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for pos, (name, item) in enumerate(vars(record).items()):
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if isinstance(item, Signal):
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if item == sig:
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# Two first pos are name and layout
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del record.layout[pos-2]
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delattr(record, name)
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break
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def get_pll_resource(self, name):
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self.pll_used.append(name)
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self.pll_available.remove(name)
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print('Pll used : ' + str(self.pll_used))
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print('Pll pll_available: ' + str(self.pll_available))
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def get_free_pll_resource(self):
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return self.pll_available[0]
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@ -0,0 +1,194 @@
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# RGMII PHY for 7-Series Xilinx FPGA
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from liteeth.common import *
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from liteeth.phy.common import *
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class LiteEthPHYRGMIITX(Module):
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def __init__(self, platform, pads):
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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# # #
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name = platform.get_pin_name(pads.tx_data)
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pad = platform.get_pin_location(pads.tx_data)
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name = 'auto_' + name
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tx_data_d1 = []
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tx_data_d2 = []
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# This a workaround, we could use signals with 4 bits but there is
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# a problem with the Python API that prevents it
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#tx_data_d1 = platform.add_iface_io(name + '_HI', 4)
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#tx_data_d2 = platform.add_iface_io(name + '_LO', 4)
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for i in range(4):
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tx_data_d1.append(platform.add_iface_io(name + str(i) + '_HI'))
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tx_data_d2.append(platform.add_iface_io(name + str(i) + '_LO'))
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block = {'type':'GPIO',
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'mode':'OUTPUT',
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'name':name + str(i),
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#'name':name,
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'location':[pad[i]],
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'size':1,
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#'location':pad,
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#'size':4,
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'out_reg':'DDIO_RESYNC',
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'out_clk_pin':'auto_eth_tx_clk', # -------------------------- TODO
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'is_inclk_inverted':False
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.del_record_signal(pads, pads.tx_data)
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#self.comb += pads.tx_ctl.eq(sink.valid)
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#self.comb += tx_data_d1.eq(sink.data[0:4])
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#self.comb += tx_data_d2.eq(sink.data[4:8])
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#self.comb += sink.ready.eq(1)
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self.comb += [ pads.tx_ctl.eq(sink.valid),
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tx_data_d1[0].eq(sink.data[0]),
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tx_data_d1[1].eq(sink.data[1]),
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tx_data_d1[2].eq(sink.data[2]),
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tx_data_d1[3].eq(sink.data[3]),
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tx_data_d2[0].eq(sink.data[4]),
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tx_data_d2[1].eq(sink.data[5]),
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tx_data_d2[2].eq(sink.data[6]),
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tx_data_d2[3].eq(sink.data[7]),
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sink.ready.eq(1),
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]
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class LiteEthPHYRGMIIRX(Module):
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def __init__(self, platform, pads):
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self.source = source = stream.Endpoint(eth_phy_description(8))
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# # #
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rx_ctl_d = Signal()
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rx_data = Signal(8)
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# pads.rx_ctl can't be connected to a special GPIO (DDIO) because
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# of this board layout.
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# Add a DDIO_RESYNC input block with 'auto_eth_rx_clk' as clock
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name = platform.get_pin_name(pads.rx_data)
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pad = platform.get_pin_location(pads.rx_data)
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name = 'auto_' + name
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rx_data_d1 = []
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rx_data_d2 = []
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# This a workaround, we could use signals with 4 bits but there is
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# a problem with the Python API that prevents it
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for i in range(4):
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rx_data_d1.append(platform.add_iface_io(name + str(i) + '_HI'))
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rx_data_d2.append(platform.add_iface_io(name + str(i) + '_LO'))
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block = {'type':'GPIO',
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'mode':'INPUT',
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'name':name + str(i),
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'location':[pad[i]],
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'size':1,
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'in_reg':'DDIO_RESYNC',
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'in_clk_pin':'auto_eth_rx_clk',
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'is_inclk_inverted':False
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.del_record_signal(pads, pads.rx_data)
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self.comb += rx_data.eq(Cat(rx_data_d1[0], rx_data_d1[1], rx_data_d1[2], rx_data_d1[3],
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rx_data_d2[0], rx_data_d2[1], rx_data_d2[2], rx_data_d2[3]))
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self.sync += rx_ctl_d.eq(pads.rx_ctl)
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last = Signal()
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self.comb += last.eq(~pads.rx_ctl & rx_ctl_d)
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self.sync += [
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source.valid.eq(pads.rx_ctl),
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source.data.eq(rx_data)
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]
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self.comb += source.last.eq(last)
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class LiteEthPHYRGMIICRG(Module, AutoCSR):
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def __init__(self, platform, clock_pads, with_hw_init_reset, tx_delay=2e-9, hw_reset_cycles=256):
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self._reset = CSRStorage()
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# # #
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# Clocks
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.clock_domains.cd_eth_tx_delayed = ClockDomain(reset_less=True)
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# Add a GPIO block with clock input property
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# Add a input 'auto_eth_rx_clk' to the top.v
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clkrx = platform.add_iface_io('auto_eth_rx_clk')
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block = {'type':'GPIO',
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'size':1,
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# Get the location from the original resource
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'location': platform.get_pin_location(clock_pads.rx)[0],
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'name':platform.get_pin_name(clkrx),
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'mode':'INPUT_CLK'
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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self.comb += self.cd_eth_rx.clk.eq(clkrx)
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clktx = platform.add_iface_io('auto_eth_tx_delayed_clk')
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block = {'type':'GPIO',
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'size':1,
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# Get the location from the original resource
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'location': platform.get_pin_location(clock_pads.tx)[0],
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'name':platform.get_pin_name(clktx),
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'mode':'OUTPUT_CLK'
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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self.comb += clktx.eq(self.cd_eth_tx.clk)
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self.submodules.pll = pll = TRIONPLL(platform)
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# Internal clock must come from a named signal
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pll.register_clkin(None, 125e6, name='auto_eth_rx_clk')
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pll.create_clkout(None, 125e6, phase=90, name='auto_eth_tx_delayed_clk')
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pll.create_clkout(None, 125e6, name='auto_eth_tx_clk')
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platform.delete(clock_pads)
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## Reset
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#self.reset = reset = Signal()
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#if with_hw_init_reset:
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# self.submodules.hw_reset = LiteEthPHYHWReset(cycles=hw_reset_cycles)
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# self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
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#else:
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# self.comb += reset.eq(self._reset.storage)
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#if hasattr(clock_pads, "rst_n"):
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# self.comb += clock_pads.rst_n.eq(~reset)
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#self.specials += [
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# AsyncResetSynchronizer(self.cd_eth_tx, reset),
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# AsyncResetSynchronizer(self.cd_eth_rx, reset),
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#]
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class LiteEthPHYRGMII(Module, AutoCSR):
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dw = 8
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tx_clk_freq = 125e6
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rx_clk_freq = 125e6
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||||
def __init__(self, platform, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9,
|
||||
iodelay_clk_freq=200e6, hw_reset_cycles=256):
|
||||
self.submodules.crg = LiteEthPHYRGMIICRG(platform, clock_pads, with_hw_init_reset, tx_delay, hw_reset_cycles)
|
||||
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(platform, pads))
|
||||
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(platform, pads))
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
|
||||
#if hasattr(pads, "mdc"):
|
||||
# self.submodules.mdio = LiteEthPHYMDIO(pads)
|
||||
|
|
@ -192,6 +192,12 @@ class ConstraintManager:
|
|||
|
||||
def delete(self, signal):
|
||||
for res, obj in self.matched:
|
||||
if isinstance(signal, Record):
|
||||
if isinstance(obj, Signal):
|
||||
continue
|
||||
else:
|
||||
if isinstance(obj, Record):
|
||||
continue
|
||||
if obj == signal:
|
||||
self.matched.remove((res, obj))
|
||||
|
||||
|
|
@ -280,12 +286,14 @@ class ConstraintManager:
|
|||
if has_subsignals:
|
||||
for element in resource[2:]:
|
||||
if isinstance(element, Subsignal):
|
||||
sig = getattr(obj, element.name)
|
||||
pins, others = _separate_pins(top_constraints +
|
||||
element.constraints)
|
||||
pins = self.connector_manager.resolve_identifiers(pins)
|
||||
r.append((sig, pins, others,
|
||||
(name, number, element.name)))
|
||||
# Because we could have removed one Signal From the record
|
||||
if hasattr(obj, element.name):
|
||||
sig = getattr(obj, element.name)
|
||||
pins, others = _separate_pins(top_constraints +
|
||||
element.constraints)
|
||||
pins = self.connector_manager.resolve_identifiers(pins)
|
||||
r.append((sig, pins, others,
|
||||
(name, number, element.name)))
|
||||
else:
|
||||
pins, others = _separate_pins(top_constraints)
|
||||
pins = self.connector_manager.resolve_identifiers(pins)
|
||||
|
|
|
|||
|
|
@ -53,33 +53,44 @@ class TRIONPLL(Module):
|
|||
|
||||
self.platform.toolchain.ifacewriter.blocks.append(block)
|
||||
|
||||
def register_clkin(self, clkin, freq):
|
||||
def register_clkin(self, clkin, freq, name= ''):
|
||||
block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
|
||||
|
||||
# If clkin has resource, PLL clock input is EXTERNAL
|
||||
# When PLL clock is external, it must not be present in the top file
|
||||
# Add a test on clkin resource here
|
||||
block['input_clock_name'] = self.platform.get_pin_name(clkin)
|
||||
pin_name = self.platform.get_pin_location(clkin)
|
||||
|
||||
self.platform.delete(clkin)
|
||||
# If clkin has a pin number, PLL clock input is EXTERNAL
|
||||
if self.platform.get_pin_location(clkin):
|
||||
|
||||
pad_name = self.platform.get_pin_location(clkin)
|
||||
self.platform.delete(clkin)
|
||||
|
||||
#tpl = "create_clock -name {clk} -period {period} [get_ports {{{clk}}}]"
|
||||
#sdc = self.platform.toolchain.additional_sdc_commands
|
||||
#sdc.append(tpl.format(clk=block['input_clock_name'], period=1/freq))
|
||||
#tpl = "create_clock -name {clk} -period {period} [get_ports {{{clk}}}]"
|
||||
#sdc = self.platform.toolchain.additional_sdc_commands
|
||||
#sdc.append(tpl.format(clk=block['input_clock_name'], period=1/freq))
|
||||
|
||||
parser = EfinixDbParser(self.platform.efinity_path, self.platform.device)
|
||||
(pll_res, clock_no) = parser.get_pll_inst_from_pin(pin_name)
|
||||
parser = EfinixDbParser(self.platform.efinity_path, self.platform.device)
|
||||
try:
|
||||
(pll_res, clock_no) = parser.get_pll_inst_from_pin(pad_name)
|
||||
except:
|
||||
self.logger.error("Cannot find a pll with {} as input".format(pad_name))
|
||||
quit()
|
||||
|
||||
block['input_clock'] = 'EXTERNAL'
|
||||
block['resource'] = pll_res
|
||||
block['clock_no'] = clock_no
|
||||
self.logger.info("Clock source: {}, using EXT_CLK{}".format(block['input_clock'], clock_no))
|
||||
self.platform.get_pll_resource(pll_res)
|
||||
else:
|
||||
block['input_clock'] = 'INTERNAL'
|
||||
block['resource'] = self.platform.get_free_pll_resource()
|
||||
block['input_signal'] = name
|
||||
self.logger.info("Clock source: {}".format(block['input_clock']))
|
||||
|
||||
block['input_clock'] = 'EXTERNAL'
|
||||
block['input_freq'] = freq
|
||||
block['resource'] = pll_res
|
||||
block['clock_no'] = clock_no
|
||||
|
||||
self.logger.info("Using {}".format(pll_res))
|
||||
self.logger.info("Clock source: {}, using EXT_CLK{}".format(block['input_clock'], clock_no))
|
||||
self.logger.info("Using {}".format(block['resource']))
|
||||
|
||||
def create_clkout(self, cd, freq, phase=0, margin=1e-2, name='', with_reset=False, user_clk=True):
|
||||
def create_clkout(self, cd, freq, phase=0, margin=1e-2, name='', with_reset=False):
|
||||
assert self.nclkouts < self.nclkouts_max
|
||||
|
||||
if name != '':
|
||||
|
|
@ -87,7 +98,7 @@ class TRIONPLL(Module):
|
|||
else:
|
||||
clk_out_name = '{}_CLKOUT{}'.format(self.pll_name, self.nclkouts)
|
||||
|
||||
if user_clk == True:
|
||||
if cd != None:
|
||||
self.platform.add_extension([(clk_out_name, 0, Pins(1))])
|
||||
tmp = self.platform.request(clk_out_name)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue