Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ddrphy: reads OK, write data coming out 1/2 cycle too late

This commit is contained in:
Sebastien Bourdeauducq 2012-02-24 15:05:52 +01:00
parent a363eb4a36
commit 17b2588321
2 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
software/bios/ddrinit.c
View File

@ -60,8 +60,8 @@ static void init_sequence(void)
CSR_DFII_BA_P0 = 0; CSR_DFII_BA_P0 = 0;
/* Load Mode Register */ /* Load Mode Register */
//setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */ setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
setaddr(0x0162); /* Reset DLL, CL=2.5, BL=4 */ //setaddr(0x0162); /* Reset DLL, CL=2.5, BL=4 */
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
cdelay(200); cdelay(200);
@ -77,8 +77,8 @@ static void init_sequence(void)
} }
/* Load Mode Register */ /* Load Mode Register */
//setaddr(0x0032); /* CL=3, BL=4 */ setaddr(0x0032); /* CL=3, BL=4 */
setaddr(0x0062); /* CL=2.5, BL=4 */ //setaddr(0x0062); /* CL=2.5, BL=4 */
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
cdelay(200); cdelay(200);
} }

32
verilog/s6ddrphy/s6ddrphy.v
View File

@ -129,7 +129,7 @@ reg r_dfi_ras_n_p1;
reg r_dfi_cas_n_p1; reg r_dfi_cas_n_p1;
reg r_dfi_we_n_p1; reg r_dfi_we_n_p1;
always @(posedge sys_clk) begin always @(posedge clk2x_270) begin
r_dfi_address_p0 <= dfi_address_p0; r_dfi_address_p0 <= dfi_address_p0;
r_dfi_bank_p0 <= dfi_bank_p0; r_dfi_bank_p0 <= dfi_bank_p0;
r_dfi_cs_n_p0 <= dfi_cs_n_p0; r_dfi_cs_n_p0 <= dfi_cs_n_p0;
@ -149,14 +149,6 @@ end
always @(posedge clk2x_270) begin always @(posedge clk2x_270) begin
if(phase_sel) begin if(phase_sel) begin
sd_a <= r_dfi_address_p1;
sd_ba <= r_dfi_bank_p1;
sd_cs_n <= r_dfi_cs_n_p1;
sd_cke <= r_dfi_cke_p1;
sd_ras_n <= r_dfi_ras_n_p1;
sd_cas_n <= r_dfi_cas_n_p1;
sd_we_n <= r_dfi_we_n_p1;
end else begin
sd_a <= r_dfi_address_p0; sd_a <= r_dfi_address_p0;
sd_ba <= r_dfi_bank_p0; sd_ba <= r_dfi_bank_p0;
sd_cs_n <= r_dfi_cs_n_p0; sd_cs_n <= r_dfi_cs_n_p0;
@ -164,6 +156,14 @@ always @(posedge clk2x_270) begin
sd_ras_n <= r_dfi_ras_n_p0; sd_ras_n <= r_dfi_ras_n_p0;
sd_cas_n <= r_dfi_cas_n_p0; sd_cas_n <= r_dfi_cas_n_p0;
sd_we_n <= r_dfi_we_n_p0; sd_we_n <= r_dfi_we_n_p0;
end else begin
sd_a <= r_dfi_address_p1;
sd_ba <= r_dfi_bank_p1;
sd_cs_n <= r_dfi_cs_n_p1;
sd_cke <= r_dfi_cke_p1;
sd_ras_n <= r_dfi_ras_n_p1;
sd_cas_n <= r_dfi_cas_n_p1;
sd_we_n <= r_dfi_we_n_p1;
end end
end end
@ -340,15 +340,15 @@ endgenerate
* DQ/DQS/DM control * DQ/DQS/DM control
*/ */
reg r_dfi_wrdata_en_p1; reg r_dfi_wrdata_en;
always @(posedge sys_clk)
r_dfi_wrdata_en_p1 <= dfi_wrdata_en_p1;
reg r2_dfi_wrdata_en_p1;
always @(posedge clk2x_270) always @(posedge clk2x_270)
r2_dfi_wrdata_en_p1 <= r_dfi_wrdata_en_p1; r_dfi_wrdata_en <= dfi_wrdata_en_p1;
assign drive_dqs = r2_dfi_wrdata_en_p1; reg r2_dfi_wrdata_en;
always @(posedge clk2x_270)
r2_dfi_wrdata_en <= r_dfi_wrdata_en;
assign drive_dqs = r2_dfi_wrdata_en;
assign drive_dq = dfi_wrdata_en_p1; assign drive_dq = dfi_wrdata_en_p1;
wire rddata_valid; wire rddata_valid;