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boards/platforms/sp605: apply same simplifications than on others platforms

This commit is contained in:
Florent Kermarrec 2019-04-23 11:21:55 +02:00
parent 24bf02934e
commit 17b6164cd9
1 changed files with 14 additions and 26 deletions
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38
litex/boards/platforms/sp605.py
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@ -1,22 +1,22 @@
# This file is Copyright (c) 2019 Michael Betz <michibetz@gmail.com> # This file is Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
# License: BSD # License: BSD
from litex.build.generic_platform import Pins, IOStandard, Subsignal from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, iMPACT from litex.build.xilinx import XilinxPlatform, iMPACT
_io = [ _io = [
# 4 LEDs above PCIE finger ("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")),
("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")), # DS3 ("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")),
("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")), # DS4 ("user_led", 2, Pins("D21"), IOStandard("LVCMOS25")),
("user_led", 2, Pins("D21"), IOStandard("LVCMOS25")), # DS5 ("user_led", 3, Pins("W15"), IOStandard("LVCMOS25")),
("user_led", 3, Pins("W15"), IOStandard("LVCMOS25")), # DS6
("user_led", 4, Pins("V19"), IOStandard("LVCMOS25")), # DS7 (FPGA_AWAKE)
("user_btn", 0, Pins("F3"), IOStandard("LVCMOS25")), ("user_btn", 0, Pins("F3"), IOStandard("LVCMOS25")),
("user_btn", 1, Pins("G6"), IOStandard("LVCMOS25")), ("user_btn", 1, Pins("G6"), IOStandard("LVCMOS25")),
("user_btn", 2, Pins("F5"), IOStandard("LVCMOS25")), ("user_btn", 2, Pins("F5"), IOStandard("LVCMOS25")),
("user_btn", 3, Pins("C1"), IOStandard("LVCMOS25")), ("user_btn", 3, Pins("C1"), IOStandard("LVCMOS25")),
("cpu_reset", 0, Pins("H8"), IOStandard("LVCMOS25")), ("cpu_reset", 0, Pins("H8"), IOStandard("LVCMOS25")),
("serial", 0, ("serial", 0,
Subsignal("cts", Pins("F19")), Subsignal("cts", Pins("F19")),
Subsignal("rts", Pins("F18")), Subsignal("rts", Pins("F18")),
@ -24,11 +24,13 @@ _io = [
Subsignal("rx", Pins("H17")), Subsignal("rx", Pins("H17")),
IOStandard("LVCMOS25") IOStandard("LVCMOS25")
), ),
("clk200", 0, ("clk200", 0,
Subsignal("p", Pins("K21")), Subsignal("p", Pins("K21")),
Subsignal("n", Pins("K22")), Subsignal("n", Pins("K22")),
IOStandard("LVDS_25") IOStandard("LVDS_25")
), ),
("eth_clocks", 0, ("eth_clocks", 0,
# Subsignal("tx", Pins("L20")), # Comment to force GMII 1G only mode # Subsignal("tx", Pins("L20")), # Comment to force GMII 1G only mode
Subsignal("gtx", Pins("AB7")), Subsignal("gtx", Pins("AB7")),
@ -148,28 +150,14 @@ _connectors = [
"P": "C11", "P": "C11",
"N": "D11" "N": "D11"
}), }),
] ]
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk200" default_clk_name = "clk200"
default_clk_period = 5.0 default_clk_period = 5.0
def __init__(self, toolchain="ise"): def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise")
toolchain=toolchain)
# self.toolchain.bitstream_commands = \
# ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
# self.toolchain.additional_commands = \
# ["write_cfgmem -force -format bin -interface spix4 -size 16 "
# "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self, programmer="xc3sprog"): def create_programmer(self):
if programmer == "xc3sprog":
return XC3SProg("xpc", p=1)
elif programmer == "impact":
return iMPACT() return iMPACT()
else:
raise ValueError("{} programmer is not supported"
.format(programmer))