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fhdl/verilog: optionally disable clock domain creation

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This commit is contained in:
Sebastien Bourdeauducq 2013-03-18 18:45:19 +01:00
parent af4eb02551
commit 17f2b17654
1 changed files with 7 additions and 3 deletions
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10
migen/fhdl/verilog.py
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@ -258,6 +258,7 @@ def _printinit(f, ios, ns):
def convert(f, ios=None, name="top",
return_ns=False,
special_overrides=dict(),
create_clock_domains=True,
display_run=False):
if not isinstance(f, Fragment):
f = f.get_fragment()
@ -268,9 +269,12 @@ def convert(f, ios=None, name="top",
try:
f.clock_domains[cd_name]
except KeyError:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
raise KeyError("Unresolved clock domain: '"+cd_name+"'")
_insert_resets(f)
f = lower_basics(f)