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build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation.

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This commit is contained in:
Florent Kermarrec 2018-12-20 10:33:32 +01:00
parent b6c98cab0d
commit 180912a7a3
4 changed files with 29 additions and 5 deletions
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10
litex/build/sim/core/sim.c
View file

@ -32,6 +32,7 @@ struct session_list_s {
};
struct session_list_s *sesslist=NULL;
struct event_base *base=NULL;
static int litex_sim_initialize_all(void **dut, void *base)
{
@ -175,7 +176,6 @@ static void cb(int sock, short which, void *arg)
tv.tv_usec = 0;
int i;
for(i = 0; i < 1000; i++)
{
for(s = sesslist; s; s=s->next)
@ -192,6 +192,9 @@ static void cb(int sock, short which, void *arg)
}
}
if (litex_sim_got_finish())
event_base_loopbreak(base);
if (!evtimer_pending(ev, NULL)) {
event_del(ev);
evtimer_add(ev, &tv);
@ -201,7 +204,6 @@ static void cb(int sock, short which, void *arg)
int main()
{
void *vdut=NULL;
struct event_base *base=NULL;
struct timeval tv;
int ret;
@ -235,8 +237,10 @@ int main()
tv.tv_usec = 0;
ev = event_new(base, -1, EV_PERSIST, cb, vdut);
event_add(ev, &tv);
event_base_dispatch(base);
#if VM_COVERAGE
litex_sim_coverage_dump();
#endif
out:
return ret;
}

11
litex/build/sim/core/veril.cpp
View file

@ -32,6 +32,17 @@ extern "C" void litex_sim_tracer_dump()
tfp->dump(ticks++);
}
extern "C" int litex_sim_got_finish()
{
return Verilated::gotFinish();
}
#if VM_COVERAGE
extern "C" void litex_sim_coverage_dump()
{
VerilatedCov::write("dut.cov");
}
#endif
vluint64_t main_time = 0;
double sc_time_stamp()

8
litex/build/sim/core/veril.h
View file

@ -7,10 +7,18 @@
extern "C" void litex_sim_eval(void *vdut);
extern "C" void litex_sim_init_tracer(void *vdut);
extern "C" void litex_sim_tracer_dump();
extern "C" int litex_sim_got_finish();
#if VM_COVERAGE
extern "C" void litex_sim_coverage_dump();
#endif
#else
void litex_sim_eval(void *vdut);
void litex_sim_init_tracer(void *vdut);
void litex_sim_tracer_dump();
int litex_sim_got_finish();
#if VM_COVERAGE
void litex_sim_coverage_dump();
#endif
#endif
#endif

1
litex/build/sim/verilator.py
View file

@ -160,6 +160,7 @@ def _run_sim(build_name, as_root=False):
if r != 0:
raise OSError("Subprocess failed")
except:
pass
if sys.platform != "win32":
termios.tcsetattr(sys.stdin.fileno(), termios.TCSAFLUSH, termios_settings)