fhdl/specials: MemoryPort.clock should always be a ClockSignal

2015-09-19 23:21:24 +08:00 · 2015-09-19 23:21:24 +08:00 · 1861ae9d01
parent 262fd50677
commit 1861ae9d01
1 changed files with 1 additions and 4 deletions
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@ -193,10 +193,7 @@ class _MemoryPort(Special):
        self.re = re
        self.we_granularity = we_granularity
        self.mode = mode
-        if isinstance(clock_domain, str):
-            self.clock = ClockSignal(clock_domain)
-        else:
-            self.clock = clock_domain
+        self.clock = ClockSignal(clock_domain)

    def iter_expressions(self):
        for attr, target_context in [