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fhdl/specials: MemoryPort.clock should always be a ClockSignal

This commit is contained in:
Sebastien Bourdeauducq 2015-09-19 23:21:24 +08:00
parent 262fd50677
commit 1861ae9d01
1 changed files with 1 additions and 4 deletions
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3
migen/fhdl/specials.py
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@ -193,10 +193,7 @@ class _MemoryPort(Special):
self.re = re self.re = re
self.we_granularity = we_granularity self.we_granularity = we_granularity
self.mode = mode self.mode = mode
if isinstance(clock_domain, str):
self.clock = ClockSignal(clock_domain) self.clock = ClockSignal(clock_domain)
else:
self.clock = clock_domain
def iter_expressions(self): def iter_expressions(self):
for attr, target_context in [ for attr, target_context in [