Merge pull request #2104 from andelf/fix/ws2812-of-1-led
Fixes #2103: calculate memory depth for WS2812
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18714dfca3
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@ -137,7 +137,8 @@ class WS2812(LiteXModule):
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self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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else:
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# Memory.
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mem = Memory(32, nleds, init=init)
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mem_depth = max(nleds, 2)
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mem = Memory(32, mem_depth, init=init)
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port = mem.get_port()
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self.specials += mem, port
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@ -13,6 +13,7 @@ from litex.soc.cores.led import WS2812
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class TestWS2812(unittest.TestCase):
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test_clk_freqs = [75e6, 50e6, 25e6]
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test_led_data = [0x100000, 0x200000, 0x300000, 0x400000, 0x500000, 0x600000, 0x700000, 0x800000, 0x900000]
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def generator(self, dut, led_signal, led_data, sys_clk_freq, iterations):
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# Error Margin from WS2812 datasheet.
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@ -71,17 +72,21 @@ class TestWS2812(unittest.TestCase):
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return ( int(x) for x in bin(num)[2:].zfill(length) )
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def run_test(self, revision, sys_clk_freq):
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def run_test(self, revision, sys_clk_freq, led_data):
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led_signal = Signal()
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led_data = [0x100000, 0x200000, 0x300000, 0x400000, 0x500000, 0x600000, 0x700000, 0x800000, 0x900000]
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iterations = 2
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dut = WS2812(led_signal, len(led_data), sys_clk_freq, revision=revision, init=led_data)
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run_simulation(dut, self.generator(dut, led_signal, led_data, sys_clk_freq, iterations), vcd_name="sim.vcd")
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def test_WS2812_old(self):
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for sys_clk_freq in self.test_clk_freqs:
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self.run_test("old", sys_clk_freq)
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self.run_test("old", sys_clk_freq, self.test_led_data)
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def test_WS2812_new(self):
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for sys_clk_freq in self.test_clk_freqs:
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self.run_test("new", sys_clk_freq)
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self.run_test("new", sys_clk_freq, self.test_led_data)
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def test_WS2812_1led(self):
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led_data = [0x100000]
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for sys_clk_freq in self.test_clk_freqs:
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self.run_test("old", sys_clk_freq, led_data)
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