Add Versa ECP5-5G Platform.
This commit is contained in:
Sergiusz Bazanski
parent
0894f9e6f7
commit
1885e50d54
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# This file is Copyright (c) 2017 Serge 'q3k' Bazanski <serge@bazanski.pl>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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_io = [
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("clk100", 0, Pins("P3"), IOStandard("LVDS")),
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("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
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("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
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("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
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("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")),
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("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
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("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
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("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
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("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
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("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
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("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
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("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
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("serial", 0,
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Subsignal("tx", Pins("A12"), IOStandard("LVCMOS33")), # X4 IO0
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Subsignal("rx", Pins("A13"), IOStandard("LVCMOS33")), # X4 IO1
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("P19")),
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Subsignal("rx", Pins("L20")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("U17")),
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Subsignal("mdio", Pins("U18")),
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Subsignal("mdc", Pins("T18")),
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Subsignal("rx_ctl", Pins("U19")),
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Subsignal("rx_data", Pins("T20 U20 T19 R18")),
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Subsignal("tx_ctl", Pins("R20")),
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Subsignal("tx_data", Pins("N19 N20 P18 P20")),
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IOStandard("LVCMOS25")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("C20")),
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Subsignal("rx", Pins("J19")),
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IOStandard("LVCMOS25")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("F20")),
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Subsignal("mdio", Pins("H20")),
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Subsignal("mdc", Pins("G19")),
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Subsignal("rx_ctl", Pins("F19")),
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Subsignal("rx_data", Pins("G18 G16 H18 H17")),
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Subsignal("tx_ctl", Pins("E19")),
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Subsignal("tx_data", Pins("J17 J16 D19 D20")),
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IOStandard("LVCMOS25")
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),
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]
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class Platform(LatticePlatform):
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default_clk_name = "clk100"
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default_clk_period = 10
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def __init__(self, **kwargs):
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LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, **kwargs)
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
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except ConstraintError:
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pass
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def create_programmer(self):
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_xcf_template = """
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<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="3.4.1">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>ECP5UM5G</Family>
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<Name>LFE5UM5G-45F</Name>
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<IDCode>0x81112043</IDCode>
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<File>{bitstream_file}</File>
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<Operation>Fast Program</Operation>
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</Device>
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<Device>
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<SelectedProg value="FALSE"/>
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<Pos>2</Pos>
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<Vendor>Lattice</Vendor>
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<Family>ispCLOCK</Family>
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<Name>ispPAC-CLK5406D</Name>
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<IDCode>0x00191043</IDCode>
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<Operation>Erase,Program,Verify</Operation>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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</Device>
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<VerifyUsercode value="FALSE"/>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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<USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
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</CableOptions>
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</ispXCF>
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"""
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return LatticeProgrammer(_xcf_template)
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