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framebuffer/phy: fix DVI clocking

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This commit is contained in:
Sebastien Bourdeauducq 2013-09-17 19:28:18 +02:00
parent e6e04a2e3a
commit 189803416b
1 changed files with 19 additions and 12 deletions
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31
milkymist/framebuffer/phy.py
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@ -1,6 +1,7 @@
from migen.fhdl.std import * from migen.fhdl.std import *
from migen.genlib.record import Record from migen.genlib.record import Record
from migen.genlib.fifo import AsyncFIFO from migen.genlib.fifo import AsyncFIFO
from migen.genlib.cdc import MultiReg
from migen.bank.description import * from migen.bank.description import *
from migen.flow.actor import * from migen.flow.actor import *
@ -73,7 +74,7 @@ class _Clocking(Module, AutoCSR):
pix_progdone = Signal() pix_progdone = Signal()
pix_locked = Signal() pix_locked = Signal()
self.specials += Instance("DCM_CLKGEN", self.specials += Instance("DCM_CLKGEN",
p_CLKFXDV_DIVIDE=2, p_CLKFX_DIVIDE=4, p_CLKFX_MD_MAX=3.0, p_CLKFX_MULTIPLY=2, p_CLKFXDV_DIVIDE=2, p_CLKFX_DIVIDE=4, p_CLKFX_MD_MAX=1.0, p_CLKFX_MULTIPLY=2,
p_CLKIN_PERIOD=20.0, p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE", p_CLKIN_PERIOD=20.0, p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
i_CLKIN=ClockSignal("base50"), o_CLKFX=clk_pix_unbuffered, i_CLKIN=ClockSignal("base50"), o_CLKFX=clk_pix_unbuffered,
@ -148,19 +149,25 @@ class _Clocking(Module, AutoCSR):
] ]
# Drive VGA/DVI clock pads # Drive VGA/DVI clock pads
pix_clk_io = Signal()
self.specials += Instance("ODDR2",
p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
o_Q=pix_clk_io,
i_C0=ClockSignal("pix"),
i_C1=~ClockSignal("pix"),
i_CE=1, i_D0=1, i_D1=0,
i_R=0, i_S=0)
if pads_vga is not None: if pads_vga is not None:
self.comb += pads_vga.clk.eq(pix_clk_io) self.specials += Instance("ODDR2",
p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
o_Q=pads_vga.clk,
i_C0=ClockSignal("pix"),
i_C1=~ClockSignal("pix"),
i_CE=1, i_D0=1, i_D1=0,
i_R=0, i_S=0)
if pads_dvi is not None: if pads_dvi is not None:
self.specials += Instance("OBUFDS", i_I=pix_clk_io, dvi_clk_se = Signal()
o_O=pads.clk_p, o_OB=pads.clk_n) self.specials += Instance("ODDR2",
p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
o_Q=dvi_clk_se,
i_C0=ClockSignal("pix"),
i_C1=~ClockSignal("pix"),
i_CE=1, i_D0=1, i_D1=0,
i_R=0, i_S=0)
self.specials += Instance("OBUFTDS", i_I=dvi_clk_se,
o_O=pads_dvi.clk_p, o_OB=pads_dvi.clk_n)
class Driver(Module, AutoCSR): class Driver(Module, AutoCSR):
def __init__(self, pads_vga, pads_dvi): def __init__(self, pads_vga, pads_dvi):