interconnect/stream: cleanup imports/idents
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@ -4,11 +4,9 @@
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# License: BSD
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import math
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from copy import copy
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from migen import *
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from migen.util.misc import xdir
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from migen.genlib.record import *
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from migen.genlib import fifo
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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@ -146,7 +144,7 @@ class PipelinedActor(BinaryActor):
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last_n.eq(last)
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)
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first = first_n
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last = last_n
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last = last_n
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self.comb += [
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source.first.eq(first),
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source.last.eq(last)
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@ -156,12 +154,12 @@ class PipelinedActor(BinaryActor):
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class _FIFOWrapper(Module):
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def __init__(self, fifo_class, layout, depth):
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self.sink = Endpoint(layout)
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self.source = Endpoint(layout)
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self.sink = sink = Endpoint(layout)
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self.source = source = Endpoint(layout)
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# # #
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description = self.sink.description
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description = sink.description
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fifo_layout = [
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("payload", description.payload_layout),
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("param", description.param_layout),
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@ -169,28 +167,28 @@ class _FIFOWrapper(Module):
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("last", 1)
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]
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self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth)
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self.submodules.fifo = fifo = fifo_class(layout_len(fifo_layout), depth)
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fifo_in = Record(fifo_layout)
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fifo_out = Record(fifo_layout)
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self.comb += [
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self.fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(self.fifo.dout)
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fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo.dout)
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]
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self.comb += [
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self.sink.ready.eq(self.fifo.writable),
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self.fifo.we.eq(self.sink.valid),
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fifo_in.first.eq(self.sink.first),
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fifo_in.last.eq(self.sink.last),
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fifo_in.payload.eq(self.sink.payload),
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fifo_in.param.eq(self.sink.param),
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sink.ready.eq(fifo.writable),
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fifo.we.eq(sink.valid),
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fifo_in.first.eq(sink.first),
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fifo_in.last.eq(sink.last),
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fifo_in.payload.eq(sink.payload),
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fifo_in.param.eq(sink.param),
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self.source.valid.eq(self.fifo.readable),
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self.source.first.eq(fifo_out.first),
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self.source.last.eq(fifo_out.last),
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self.source.payload.eq(fifo_out.payload),
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self.source.param.eq(fifo_out.param),
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self.fifo.re.eq(self.source.ready)
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source.valid.eq(fifo.readable),
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source.first.eq(fifo_out.first),
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source.last.eq(fifo_out.last),
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source.payload.eq(fifo_out.payload),
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source.param.eq(fifo_out.param),
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fifo.re.eq(source.ready)
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]
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@ -504,7 +502,7 @@ class Gearbox(Module):
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shift_register = Signal(io_lcm)
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i_cases = {}
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i_data = Signal(i_dw)
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i_data = Signal(i_dw)
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if msb_first:
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self.comb += i_data.eq(sink.data)
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else:
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@ -514,7 +512,7 @@ class Gearbox(Module):
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self.sync += If(sink.valid & sink.ready, Case(i_count, i_cases))
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o_cases = {}
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o_data = Signal(o_dw)
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o_data = Signal(o_dw)
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for i in range(io_lcm//o_dw):
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o_cases[i] = o_data.eq(shift_register[io_lcm - o_dw*(i+1):io_lcm - o_dw*i])
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self.comb += Case(o_count, o_cases)
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@ -674,7 +672,7 @@ class Cast(CombinatorialActor):
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class Unpack(Module):
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def __init__(self, n, layout_to, reverse=False):
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self.source = source = Endpoint(layout_to)
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description_from = copy(source.description)
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description_from = Endpoint(layout_to).description
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description_from.payload_layout = pack_layout(description_from.payload_layout, n)
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self.sink = sink = Endpoint(description_from)
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@ -718,7 +716,7 @@ class Unpack(Module):
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class Pack(Module):
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def __init__(self, layout_from, n, reverse=False):
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self.sink = sink = Endpoint(layout_from)
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description_to = copy(sink.description)
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description_to = Endpoint(layout_from).description
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description_to.payload_layout = pack_layout(description_to.payload_layout, n)
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self.source = source = Endpoint(description_to)
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@ -726,7 +724,7 @@ class Pack(Module):
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demux = Signal(max=n)
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load_part = Signal()
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load_part = Signal()
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strobe_all = Signal()
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cases = {}
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for i in range(n):
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