build/efinix/efinity: Simplify/Cleanup pass and only keep mandatory information in project's xml.
This commit is contained in:
Florent Kermarrec
parent
a5356f78c3
commit
1932506373
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@ -2,7 +2,7 @@
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2015-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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@ -33,7 +33,7 @@ def get_pin_direction(fragment, platform, pinname):
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pins = platform.constraint_manager.get_io_signals()
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for pin in sorted(pins, key=lambda x: x.duid):
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# Better idea ???
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if (pinname.split('[')[0] == pin.name):
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if (pinname.split("[")[0] == pin.name):
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return pin.direction
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return "Unknown"
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@ -66,12 +66,12 @@ def _build_sdc(clocks, false_paths, vns, named_sc, build_name, additional_sdc_co
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# Generate .sdc
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tools.write_to_file("{}.sdc".format(build_name), "\n".join(sdc))
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# Peripheral configuration ------------------------------------------------------------------------
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# Peripheral configuration (.xml) ------------------------------------------------------------------
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def _create_gpio_instance(fragment, platform, sig, pins):
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l = ""
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if len(pins) > 1:
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l = ',{},0'.format(len(pins) - 1)
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l = ",{},0".format(len(pins) - 1)
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d = get_pin_direction(fragment, platform, sig)
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return 'design.create_{d}_gpio("{name}"{len})'.format(d=d, name=sig, len=l)
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@ -84,9 +84,9 @@ def _format_constraint(c, signame, fmt_r, fragment, platform):
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# IO standard property
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elif isinstance(c, IOStandard):
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prop = ""
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valid = ['3.3_V_LVTTL_/_LVCMOS', '2.5_V_LVCMOS', '1.8_V_LVCMOS']
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valid = ["3.3_V_LVTTL_/_LVCMOS", "2.5_V_LVCMOS", "1.8_V_LVCMOS"]
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if c.name in valid:
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prop = 'IO_STANDARD'
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prop = "IO_STANDARD"
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if prop == "":
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print("{} has a wrong IOStandard format [{}]".format(signame, c.name))
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@ -100,13 +100,13 @@ def _format_constraint(c, signame, fmt_r, fragment, platform):
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# Others constraints
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elif isinstance(c, Misc):
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prop = ""
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if c.misc in ['WEAK_PULLUP', 'WEAK_PULLDOWN']:
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prop = 'PULL_OPTION'
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if c.misc in ["WEAK_PULLUP", "WEAK_PULLDOWN"]:
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prop = "PULL_OPTION"
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val = c.misc
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if 'DRIVE_STRENGTH' in c.misc:
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prop = 'DRIVE_STRENGTH'
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val = c.misc.split('=')[1]
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if "DRIVE_STRENGTH" in c.misc:
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prop = "DRIVE_STRENGTH"
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val = c.misc.split("=")[1]
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if prop == "":
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# Print error, warning ??
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@ -120,7 +120,7 @@ def _format_conf_constraint(signame, pin, others, resname, fragment, platform):
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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fmt_c = [_format_constraint(c, signame, fmt_r, fragment, platform) for c in ([Pins(pin)] + others)]
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return ''.join(fmt_c)
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return "".join(fmt_c)
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def _build_iface_gpio(named_sc, named_pc, fragment, platform, excluded_ios):
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conf = []
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@ -151,146 +151,121 @@ def _build_iface_gpio(named_sc, named_pc, fragment, platform, excluded_ios):
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return "\n".join(conf)
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def _build_peri(efinity_path, build_name, partnumber, named_sc, named_pc, fragment, platform, additional_iface_commands, excluded_ios):
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def _build_peri(efinity_path, build_name, device, named_sc, named_pc, fragment, platform, additional_iface_commands, excluded_ios):
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pythonpath = ""
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header = platform.toolchain.ifacewriter.header(build_name, partnumber)
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gen = platform.toolchain.ifacewriter.generate(partnumber)
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#TODO: move this to ifacewriter
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gpio = _build_iface_gpio(named_sc, named_pc, fragment, platform, excluded_ios)
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add = '\n'.join(additional_iface_commands)
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footer = platform.toolchain.ifacewriter.footer()
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header = platform.toolchain.ifacewriter.header(build_name, device)
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gen = platform.toolchain.ifacewriter.generate(device)
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#TODO : move this to ifacewriter
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gpio = _build_iface_gpio(named_sc, named_pc, fragment, platform, excluded_ios)
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add = "\n".join(additional_iface_commands)
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footer = platform.toolchain.ifacewriter.footer()
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tools.write_to_file("iface.py", header + gen + gpio + add + footer)
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if subprocess.call([efinity_path + '/bin/python3', 'iface.py']) != 0:
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if subprocess.call([efinity_path + "/bin/python3", "iface.py"]) != 0:
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raise OSError("Error occurred during Efinity peri script execution.")
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# Project configuration ------------------------------------------------------------------------
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# Project configuration (.xml) ---------------------------------------------------------------------
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def _build_xml(family, device, timing_model, build_name, sources, additional_xml_commands):
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def _build_xml(family, device, timing_model, build_name, sources):
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now = datetime.datetime.now()
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root = et.Element('efx:project')
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# Create Project.
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root = et.Element("efx:project")
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root.attrib["xmlns:efx"] = "http://www.efinixinc.com/enf_proj"
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root.attrib["name"] = build_name
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root.attrib["location"] = str(pathlib.Path().resolve())
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root.attrib["sw_version"] = "2021.1.165.2.19" # TODO: read it from sw_version.txt
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root.attrib["last_change_date"] = f"Date : {now.strftime('%Y-%m-%d %H:%M')}"
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now = datetime.datetime.now()
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date_str = " Date: " + now.strftime("%Y-%m-%d %H:%M") + " "
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# Add Device.
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device_info = et.SubElement(root, "efx:device_info")
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et.SubElement(device_info, "efx:family", name=family)
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et.SubElement(device_info, "efx:device", name=device)
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et.SubElement(device_info, "efx:timing_model", name=timing_model)
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# Add the required attributes
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root.attrib['xmlns:efx'] = 'http://www.efinixinc.com/enf_proj'
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root.attrib['xmlns:xsi'] = "http://www.w3.org/2001/XMLSchema-instance"
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root.attrib['name'] = build_name
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root.attrib['description'] = ''
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root.attrib['last_change_date'] = date_str
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root.attrib['location'] = str(pathlib.Path().resolve())
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root.attrib['sw_version'] = '2021.1.165.2.19' # TODO: read it from sw_version.txt
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root.attrib['last_run_state'] = ''
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root.attrib['last_run_tool'] = ''
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root.attrib['last_run_flow'] = ''
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root.attrib['config_result_in_sync'] = 'sync'
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root.attrib['design_ood'] = 'sync'
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root.attrib['place_ood'] = 'sync'
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root.attrib['route_ood'] = 'sync'
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root.attrib['xsi:schemaLocation'] = 'http://www.efinixinc.com/enf_proj enf_proj.xsd'
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# Add Design Info.
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design_info = et.SubElement(root, "efx:design_info")
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et.SubElement(design_info, "efx:top_module", name=build_name)
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device_info = et.SubElement(root, 'efx:device_info')
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et.SubElement(device_info, 'efx:family', name = family)
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et.SubElement(device_info, 'efx:device', name = device)
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et.SubElement(device_info, 'efx:timing_model', name = timing_model)
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design_info = et.SubElement(root, 'efx:design_info')
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et.SubElement(design_info, "efx:top_module", name = build_name)
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# Add Design Sources.
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for filename, language, library in sources:
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if '.vh' not in filename:
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val = {'name':filename, 'version':'default', 'library':'default'}
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et.SubElement(design_info, "efx:design_file", val)
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et.SubElement(design_info, "efx:top_vhdl_arch", name = "")
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if ".vh" not in filename:
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et.SubElement(design_info, "efx:design_file", {
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"name" : filename,
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"version" : "default",
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"library" : "default",
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})
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# Add Timing Constraints.
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constraint_info = et.SubElement(root, "efx:constraint_info")
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et.SubElement(constraint_info, "efx:sdc_file", name = "{}.sdc".format(build_name))
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et.SubElement(constraint_info, "efx:sdc_file", name=f"{build_name}.sdc")
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# Add Misc Info.
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misc_info = et.SubElement(root, "efx:misc_info")
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# Add IP Info.
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ip_info = et.SubElement(root, "efx:ip_info")
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synthesis = et.SubElement(root, "efx:synthesis", tool_name="efx_map")
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for l in additional_xml_commands:
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if l[0] == 'efx_map':
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val = {'name':l[1], 'value':l[2], 'value_type':l[3]}
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et.SubElement(synthesis, "efx:param", val)
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place_and_route = et.SubElement(root, "efx:place_and_route", tool_name="efx_pnr")
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for l in additional_xml_commands:
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if l[0] == 'efx_pnr':
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val = {'name':l[1], 'value':l[2], 'value_type':l[3]}
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et.SubElement(place_and_route, "efx:param", val)
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bitstream_generation = et.SubElement(root, "efx:bitstream_generation", tool_name="efx_pgm")
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for l in additional_xml_commands:
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if l[0] == 'efx_pgm':
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val = {'name':l[1], 'value':l[2], 'value_type':l[3]}
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et.SubElement(bitstream_generation, "efx:param", val)
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xml_string = et.tostring(root, 'utf-8')
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reparsed = expatbuilder.parseString(xml_string, False)
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print_string = reparsed.toprettyxml(indent=" ")
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# Generate .xml
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tools.write_to_file("{}.xml".format(build_name), print_string)
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xml_str = et.tostring(root, "utf-8")
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xml_str = expatbuilder.parseString(xml_str, False)
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xml_str = xml_str.toprettyxml(indent=" ")
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tools.write_to_file("{}.xml".format(build_name), xml_str)
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# Efinity Toolchain --------------------------------------------------------------------------------
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class EfinityToolchain:
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attr_translate = {}
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def __init__(self, efinity_path):
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self.options = {}
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self.clocks = dict()
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self.false_paths = set()
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self.efinity_path = efinity_path
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self.additional_sdc_commands = []
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self.additional_xml_commands = [
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[ 'efx_pgm', 'io_weak_pullup', 'on', 'e_bool'],
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[ 'efx_pgm', 'oscillator_clock_divider', 'DIV8', 'e_option'],
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[ 'efx_pgm', 'enable_crc_check', 'on', 'e_bool'],
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]
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self.ifacewriter = InterfaceWriter(efinity_path)
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self.excluded_ios = []
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self.options = {}
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self.clocks = dict()
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self.false_paths = set()
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self.efinity_path = efinity_path
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self.ifacewriter = InterfaceWriter(efinity_path)
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self.excluded_ios = []
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self.additional_sdc_commands = []
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self.additional_iface_commands = []
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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run = True,
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build_dir = "build",
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build_name = "top",
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run = True,
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**kwargs):
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family = "Trion" # FIXME: Add Titanium support.
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self.ifacewriter.set_build_params(platform, build_name)
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# Create build directory
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# Create Build Directory.
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cwd = os.getcwd()
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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# Apply FullMemoryWE on design (Efiniy does not infer memories correctly otherwise).
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# Apply FullMemoryWE on Design (Efiniy does not infer memories correctly otherwise).
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FullMemoryWE()(fragment)
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# Finalize design
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# Finalize Design.
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Generate verilog
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# Generate Design.
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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v_output.write(f"{build_name}.v")
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platform.add_source(f"{build_name}.v")
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# Add Include Paths.
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if platform.verilog_include_paths:
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self.options['includ_path'] = '{' + ';'.join(platform.verilog_include_paths) + '}'
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self.options["includ_path"] = "{" + ";".join(platform.verilog_include_paths) + "}"
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os.environ['EFXPT_HOME'] = self.efinity_path + '/pt'
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os.environ["EFXPT_HOME"] = self.efinity_path + "/pt"
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# Generate design timing constraints file (.sdc)
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# Generate Design Timing Constraints file (.sdc)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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_build_sdc(
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clocks = self.clocks,
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false_paths = self.false_paths,
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@ -302,25 +277,24 @@ class EfinityToolchain:
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# Generate project file (.xml)
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_build_xml(
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family = family,
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device = platform.device,
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timing_model = platform.timing_model,
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build_name = build_name,
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sources = platform.sources,
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additional_xml_commands = self.additional_xml_commands,
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family = family,
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device = platform.device,
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timing_model = platform.timing_model,
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build_name = build_name,
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sources = platform.sources
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)
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# Generate constraints file (.peri.xml)
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# Generate peripheral file (.peri.xml)
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_build_peri(
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efinity_path = self.efinity_path,
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build_name = build_name,
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partnumber = platform.device,
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device = platform.device,
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named_sc = named_sc,
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named_pc = named_pc,
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fragment = fragment,
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platform = platform,
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additional_iface_commands = self.additional_iface_commands,
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excluded_ios = self.excluded_ios,
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excluded_ios = self.excluded_ios
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)
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# DDR doesn't have Python API so we need to configure it
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@ -395,18 +369,18 @@ class EfinityToolchain:
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# Bitstream.
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r = subprocess.call([self.efinity_path + "/bin/efx_pgm",
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"--source", f"work_pnr/{build_name}.lbf",
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"--dest", f"outflow/{build_name}.hex",
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"--device", platform.device,
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"--family", family,
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"--periph", f"outflow/{build_name}.lpf",
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"--oscillator_clock_divider", "DIV8",
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"--spi_low_power_mode", "off",
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"--io_weak_pullup", "on",
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"--enable_roms", "on",
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"--mode", "active",
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"--width", "1",
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"--enable_crc_check", "on"
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"--source", f"work_pnr/{build_name}.lbf",
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"--dest", f"outflow/{build_name}.hex",
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"--device", platform.device,
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"--family", family,
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"--periph", f"outflow/{build_name}.lpf",
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"--oscillator_clock_divider", "DIV8",
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"--spi_low_power_mode", "off",
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"--io_weak_pullup", "on",
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"--enable_roms", "on",
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"--mode", "active",
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"--width", "1",
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"--enable_crc_check", "on"
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])
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if r != 0:
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raise OSError("Error occurred during efx_pgm execution.")
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