cores: fix liteeth
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766b0bee65
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197e5cf31c
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@ -58,9 +58,11 @@ class LiteEthPHYMIIRX(Module):
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converter.sink.stb.eq(1),
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converter.sink.stb.eq(1),
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converter.sink.data.eq(pads.rx_data)
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converter.sink.data.eq(pads.rx_data)
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]
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]
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self.comb += [
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self.sync += [
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sop_set.eq(~pads.dv),
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sop_set.eq(~pads.dv),
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sop_clr.eq(pads.dv),
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sop_clr.eq(pads.dv)
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]
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self.comb += [
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converter.sink.sop.eq(sop),
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converter.sink.sop.eq(sop),
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converter.sink.eop.eq(~pads.dv)
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converter.sink.eop.eq(~pads.dv)
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]
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]
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