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soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description

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Florent Kermarrec 2020-01-02 09:41:47 +01:00
parent b65a36e7e8
commit 197edad34e
1 changed files with 2 additions and 2 deletions
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litex/soc/integration/soc_core.py
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@ -45,8 +45,8 @@ class SoCController(Module, AutoCSR):
Write a ``1`` to this register to reset the SoC.""") Write a ``1`` to this register to reset the SoC.""")
self._scratch = CSRStorage(32, reset=0x12345678, description=""" self._scratch = CSRStorage(32, reset=0x12345678, description="""
Use this register as a scratch space to verify that software read/write accesses Use this register as a scratch space to verify that software read/write accesses
to the Wishbone/CSR bus are working correctly. The initial reset value can be used to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
to verify endianness.""") can be used to verify endianness.""")
self._bus_errors = CSRStatus(32, description=""" self._bus_errors = CSRStatus(32, description="""
Total number of Wishbone bus errors (timeouts) since last reset.""") Total number of Wishbone bus errors (timeouts) since last reset.""")