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platforms/lx9_microboard,usrp_b100: fix bitgen opts
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parent
263fc47728
commit
19a6157478
2 changed files with 3 additions and 3 deletions
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@ -110,8 +110,8 @@ class Platform(XilinxPlatform):
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self.add_platform_command("""
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self.add_platform_command("""
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CONFIG VCCAUX = "3.3";
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CONFIG VCCAUX = "3.3";
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""")
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""")
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self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
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self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
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self.ise_commands = """
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self.toolchain.ise_commands = """
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promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
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promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
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"""
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"""
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@ -118,7 +118,7 @@ class Platform(XilinxPlatform):
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def __init__(self):
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def __init__(self):
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XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
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XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
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self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
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self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
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def do_finalize(self, fragment):
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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XilinxPlatform.do_finalize(self, fragment)
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