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platforms/lx9_microboard,usrp_b100: fix bitgen opts

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This commit is contained in:
Sebastien Bourdeauducq 2015-03-30 00:44:56 +08:00
parent 263fc47728
commit 19a6157478
2 changed files with 3 additions and 3 deletions
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4
mibuild/platforms/lx9_microboard.py
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@ -110,8 +110,8 @@ class Platform(XilinxPlatform):
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.ise_commands = """
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.toolchain.ise_commands = """
promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
"""

2
mibuild/platforms/usrp_b100.py
View file

@ -118,7 +118,7 @@ class Platform(XilinxPlatform):
def __init__(self):
XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)