update to comply with python-data layout
This commit is contained in:
sadullah
parent
3eb9efd64f
commit
19bb1b9b8c
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@ -1,12 +1,22 @@
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TODO: Edit
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git submodule update --init --recursive (for blackparrot pre-alpha repo)
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cd pre_alpha_release
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follow getting_started to install blackparrot
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cd ..
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source ./setEnvironment.sh #should be sourced each time you open a terminal or just add this line to bashrc
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Add $BP_TOP/external/bin to $PATH for verilator and riscv-gnu tools
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./update_BP.sh #to modify some of the files in Blackparrot repo (one-time process)
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Currently, we could simulate the LITEX-BIOS on BP processor.
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#TODO Running BIOS
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#TODO Running Linux
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#TODO Running on FPGA
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#TODO
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RISCV tool chain explanation (we currently support IA extension)
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[](https://asciinema.org/a/286568)
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@ -118,13 +118,13 @@ class BlackParrotRV64(CPU):
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@staticmethod
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def add_sources(platform, variant="standard"):
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vdir = get_data_mod("cpu", "blackparrot").data_location
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bp_litex_dir = os.path.join(vdir,"bp_litex")
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simulation = 0
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if (simulation == 1):
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filename = get_data_mod("cpu", "blackparrot").data_file(
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"flist.verilator")
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filename= os.path.join(bp_litex_dir,"flist.verilator")
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else:
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filename = get_data_mod("cpu", "blackparrot").data_file(
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"flist.fpga")
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filename= os.path.join(bp_litex_dir,"flist.fpga")
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with open(filename) as openfileobject:
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for line in openfileobject:
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temp = line
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@ -1,98 +1,24 @@
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#!/bin/bash
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## Set common environment variables
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export LITEX=$(git rev-parse --show-toplevel)
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export BP=$PWD
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cp bp_software/cce_ucode.mem /tmp/.
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cd pre-alpha-release
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TOP=$(git rev-parse --show-toplevel)
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export BP_COMMON_DIR=$TOP/bp_common
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export BP_FE_DIR=$TOP/bp_fe
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export BP_BE_DIR=$TOP/bp_be
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export BP_ME_DIR=$TOP/bp_me
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export BP_TOP_DIR=$TOP/bp_top
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export BP_EXTERNAL_DIR=$TOP/external
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export BP=$LITEX/../pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog
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export BP_LITEX_DIR=$BP/bp_litex
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export LITEX_SOFTWARE_COMPILER_RT=$LITEX/../pythondata-software-compiler_rt
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#TODO: check if BP exists and warn user
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export BP_COMMON_DIR=$BP/bp_common
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export BP_FE_DIR=$BP/bp_fe
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export BP_BE_DIR=$BP/bp_be
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export BP_ME_DIR=$BP/bp_me
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export BP_TOP_DIR=$BP/bp_top
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export BP_EXTERNAL_DIR=$BP/external
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export BASEJUMP_STL_DIR=$BP_EXTERNAL_DIR/basejump_stl
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export BP_FPGA_DIR=$TOP/bp_fpga
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## Setup CAD tools
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export LITEX_FPGA_DIR=$BP_LITEX_DIR/fpga
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export LITEX_SIMU_DIR=$BP_LITEX_DIR/simulation
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export LITEX_SOFTWARE=$BP_LITEX_DIR/software
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# If the machine you are working on is bsg_cadenv compliant, then you do not
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# need to setup the cad tools, simply put bsg_cadenv in the same root dir.
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#BSG_CADENV_DIR=$(TOP)/external/bsg_cadenv
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#-include $(BSG_CADENV_DIR)/cadenv.mk
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##SOFTWARE CHANGES##
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## Sepcify license path if needed
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#LM_LICENSE_FILE ?=
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#for a reason, provided udivmoddi4.c is not functionally correct when used with either BP or Rocket under IA extension. Another version of udivmoddi4.c is a workaround to run BIOS on these architectures.
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cp $LITEX_SOFTWARE/udivmoddi4.c $LITEX_SOFTWARE_COMPILER_RT/pythondata_software_compiler_rt/data/lib/builtins/.
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## Override tool paths if needed
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#GCC ?= gcc
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#VCS_HOME ?=
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#VCS ?= vcs
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#URG ?= urg
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#VERILATOR ?= verilator
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#DC_SHELL ?= dc_shell
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#DVE ?= dve
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#PYTHON ?= python
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## Needed for verilator g++ compilations
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export SYSTEMC_INCLUDE=$BP_EXTERNAL_DIR/include
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export SYSTEMC_LIBDIR=$BP_EXTERNAL_DIR/lib-linux64
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## Add external tools and libraries to environment
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export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR
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#:$LD_LIBRARY_PATH
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#export PATH=$(BP_EXTERNAL_DIR)/bin:$(PATH)
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#export SYN_PATH=$(BP_TOP_DIR)/syn
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#export TB_PATH=$(BP_TOP_DIR)/test/tb
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#export MEM_PATH=$(BP_COMMON_DIR)/test/mem
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#export LOG_PATH=$(BP_TOP_DIR)/syn/logs
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#export RESULTS_PATH=$(BP_TOP_DIR)/syn/results
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#export REPORT_PATH=$(BP_TOP_DIR)/syn/reports
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TB="bp_top_trace_demo"
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CFG="e_bp_single_core_cfg"
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START_PC=0x80000000
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TOLERANCE=2
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# Select CCE ROM based on CFG and Coherence Protocol
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# TODO: is there a more scalable way to do this?
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if [ $CFG = "e_bp_half_core_cfg" ]
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then
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NUM_LCE_P=1
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N_WG=64
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elif [ $CFG = "e_bp_single_core_cfg" ]
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then
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NUM_LCE_P=2
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N_WG=64
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#echo "Single Core config"
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#elif ($CFG -eq e_bp_dual_core_cfg)
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# NUM_LCE_P=4
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# N_WG=32
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#elif ($CFG -eq e_bp_quad_core_cfg)
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# NUM_LCE_P=8
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# N_WG=16
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#elif ($CFG -eq e_bp_oct_core_cfg)
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# NUM_LCE_P=16
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# N_WG=8
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#elif ($(CFG), e_bp_sexta_core_cfg)
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# NUM_LCE_P=32
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# N_WG=4
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#elif ($(CFG), e_bp_quad_core_2d_cfg)
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# NUM_LCE_P=8
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# N_WG=16
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#elif ($(CFG), e_bp_oct_core_2d_cfg)
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# NUM_LCE_P=16
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# N_WG=8
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fi
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COH_PROTO="mesi"
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CCE_MEM_PATH=$BP_ME_DIR/src/asm/roms/$COH_PROTO
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CCE_MEM=bp_cce_inst_rom_$COH_PROTO_lce$NUM_LCE_P_wg$N_WG_assoc8.mem
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#DRAMSIM_CH_CFG=DDR2_micron_16M_8b_x8_sg3E.ini
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#DRAMSIM_SYS_CFG=system.ini
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#$include $BP_COMMON_DIR/syn/Makefile.verilator
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#iinclude $(BP_COMMON_DIR)/syn/Makefile.common
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#include $(BP_COMMON_DIR)/syn/Makefile.dc
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#include $(BP_COMMON_DIR)/syn/Makefile.regress
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#include $(BP_COMMON_DIR)/syn/Makefile.vcs
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cd ../
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@ -2,7 +2,7 @@ include ../include/generated/variables.mak
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include $(SOC_DIRECTORY)/software/common.mak
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ifeq ($(CPU),blackparrot)
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BP_LIBS = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/9.2.0/
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BP_LIBS = -L$(LITEX_SOFTWARE)
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BP_FLAGS = -lgcc
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endif
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# Permit TFTP_SERVER_PORT override from shell environment / command line
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@ -353,7 +353,7 @@ def main():
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with_analyzer = args.with_analyzer,
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sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
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**soc_kwargs)
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if args.sdram_init is not None: #sdram_init
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if args.ram_init is not None: #sdram_init
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soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
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if args.with_ethernet:
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for i in range(4):
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