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Merge pull request #1549 from antmicro/msieron/vivado-verilog-include-paths-fix 

build/xilinx/vivado: fix verilog include paths
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enjoy-digital 2023-01-02 18:22:27 +01:00 committed by GitHub
parent 3dee741bac bd82a7b888
commit 19e0e2fe8d
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1 changed files with 1 additions and 1 deletions
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litex/build/xilinx/vivado.py
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@ -281,7 +281,7 @@ class XilinxVivadoToolchain(GenericToolchain):
tcl.append("\n# Synthesis\n") tcl.append("\n# Synthesis\n")
synth_cmd = f"synth_design -directive {self.vivado_synth_directive} -top {self._build_name} -part {self.platform.device}" synth_cmd = f"synth_design -directive {self.vivado_synth_directive} -top {self._build_name} -part {self.platform.device}"
if self.platform.verilog_include_paths: if self.platform.verilog_include_paths:
synth_cmd += f" -include_dirs \{{" ".join(self.platform.verilog_include_paths)}\}" synth_cmd += f" -include_dirs {{{' '.join(self.platform.verilog_include_paths)}}}"
tcl.append(synth_cmd) tcl.append(synth_cmd)
elif self._synth_mode == "yosys": elif self._synth_mode == "yosys":
tcl.append("\n# Read Yosys EDIF\n") tcl.append("\n# Read Yosys EDIF\n")