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cores/clock/create_clkout: rename clk_ce to ce, improve error reporting

This commit is contained in:
Florent Kermarrec 2020-01-24 09:06:35 +01:00
parent 7e08836062
commit 19ef19ce0d
1 changed files with 6 additions and 4 deletions
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10
litex/soc/cores/clock.py
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@ -41,7 +41,7 @@ class XilinxClocking(Module, AutoCSR):
raise ValueError
self.clkin_freq = freq
def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, clk_ce=None):
def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, ce=None):
assert self.nclkouts < self.nclkouts_max
clkout = Signal()
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
@ -57,12 +57,14 @@ class XilinxClocking(Module, AutoCSR):
self.specials += Instance("BUFG", i_I=clkout, o_O=clkout_buf)
elif buf == "bufr":
self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf)
elif buf == "bufgce" and clk_ce != None:
self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=clk_ce)
elif buf == "bufgce":
if ce is None:
raise ValueError("BUFGCE requires user to provide a clock enable ce Signal")
self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=ce)
elif buf == "bufio":
self.specials += Instance("BUFIO", i_I=clkout, o_O=clkout_buf)
else:
raise ValueError
raise ValueError("Unsupported clock buffer: {}".format(buf))
def compute_config(self):
config = {}