change export format and simplify usage
This commit is contained in:
parent
ba0382ad92
commit
1a07116ab1
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@ -1,5 +1,8 @@
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import csv
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import time
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import sys
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from miscope.host.vcd import *
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from miscope.host.truthtable import *
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class MiIoDriver():
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def __init__(self, regs, name):
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@ -20,27 +23,52 @@ class MiIoDriver():
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return self.miio_i.read()
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class MiLaDriver():
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def __init__(self, width, regs, name, config_csv=None, use_rle=True):
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def __init__(self, regs, name, csv_name=None, use_rle=True):
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self.regs = regs
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self.name = name
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self.build_mila()
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if csv:
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self.build_layout(config_csv)
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self.dat = VcdDat(width)
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self.use_rle = use_rle
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if csv_name is None:
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self.csv = name + ".csv"
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self.get_config()
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self.get_layout()
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self.build_mila()
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self.dat = VcdDat(self.width)
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def get_config(self):
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csv_reader = csv.reader(open(self.csv), delimiter=',', quotechar='#')
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for item in csv_reader:
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t, n, v = item
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if t == "config":
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setattr(self, n, int(v))
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def get_layout(self):
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self.layout = []
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csv_reader = csv.reader(open(self.csv), delimiter=',', quotechar='#')
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for item in csv_reader:
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t, n, v = item
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if t == "layout":
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self.layout.append((n, int(v)))
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def build_mila(self):
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for key, value in self.regs.d.items():
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if self.name in key:
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key.replace(self.name, "mila")
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setattr(self, key, value)
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value = 1
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for name, length in self.layout:
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setattr(self, name+"_o", value)
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value = value*(2**length)
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value = 0
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for name, length in self.layout:
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setattr(self, name+"_m", (2**length-1) << value)
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value += length
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def build_layout(self, config_csv):
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self.layout = []
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csv_reader = csv.reader(open(config_csv), delimiter=',', quotechar='#')
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for item in csv_reader:
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name, length = item
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self.layout.append((name, int(length)))
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def show_state(self, s, last=False):
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print(s, end="")
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if not last:
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print("-->", end="")
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sys.stdout.flush()
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def prog_term(self, port, trigger, mask):
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t = getattr(self, "mila_trigger_port{d}_trig".format(d=int(port)))
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@ -62,7 +90,8 @@ class MiLaDriver():
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fm.write(falling_mask)
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bm.write(both_mask)
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def prog_sum(self, datas):
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def prog_sum(self, equation):
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datas = gen_truth_table(equation)
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for adr, dat in enumerate(datas):
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self.mila_trigger_sum_prog_adr.write(adr)
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self.mila_trigger_sum_prog_dat.write(dat)
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@ -77,8 +106,13 @@ class MiLaDriver():
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def is_done(self):
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return self.mila_recorder_done.read()
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def wait_done(self):
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self.show_state("WAIT")
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while(not self.is_done()):
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time.sleep(0.1)
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def trigger(self, offset, length):
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print("T")
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self.show_state("TRIG")
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if self.use_rle:
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self.enable_rle()
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self.mila_recorder_offset.write(offset)
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@ -86,7 +120,7 @@ class MiLaDriver():
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self.mila_recorder_trigger.write(1)
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def read(self, vcd=None):
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print("R")
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self.show_state("READ", last=not vcd)
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empty = self.mila_recorder_read_empty.read()
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while(not empty):
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self.dat.append(self.mila_recorder_read_dat.read())
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@ -95,7 +129,7 @@ class MiLaDriver():
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if self.use_rle:
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self.dat = self.dat.decode_rle()
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if vcd:
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print("V")
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self.show_state("VCD", last=True)
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_vcd = Vcd()
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_vcd.add_from_layout(self.layout, self.dat)
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_vcd.write(vcd)
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@ -22,8 +22,16 @@ class Uart2Wishbone:
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self.uart.close()
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self.uart.open()
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self.uart.flushInput()
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try:
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wb.regs.uart2wb_sel.write(1)
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except:
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pass
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def close(self):
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try:
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wb.regs.uart2wb_sel.write(0)
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except:
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pass
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self.uart.close()
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def read(self, addr, burst_length=1):
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@ -161,7 +161,6 @@ class Vcd:
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def p_vars(self):
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r = ""
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for var in self.vars:
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print(var.name)
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r += "$var "
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r += var.type
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r += " "
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@ -8,6 +8,9 @@ from miscope.storage import Recorder, RunLengthEncoder
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class MiLa(Module, AutoCSR):
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def __init__(self, width, depth, ports, with_rle=False):
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self.width = width
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self.depth = depth
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self.with_rle = with_rle
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self.ports = ports
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self.sink = rec_dat(width)
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@ -30,8 +33,15 @@ class MiLa(Module, AutoCSR):
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recorder_dat_source = self.rle.source
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self.comb += recorder_dat_source.connect(recorder.dat_sink)
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def get_csv(self, dat):
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def get_csv(self, layout):
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r = ""
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for e in dat:
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r += e.backtrace[-1][0] + "," + str(flen(e)) + "\n"
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def format_line(*args):
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return ",".join(args) + "\n"
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r += format_line("config", "width", str(self.width))
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r += format_line("config", "depth", str(self.depth))
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r += format_line("config", "with_rle", str(int(self.with_rle)))
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for e in layout:
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r += format_line("layout", e.backtrace[-1][0], str(flen(e)))
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return r
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