Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

bank/csrgen: use enumerate

This commit is contained in:
Sebastien Bourdeauducq 2012-02-06 11:18:30 +01:00
parent 629e771fc0
commit 1a86f26a66
1 changed files with 5 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
migen/bank/csrgen.py
View File

@ -15,18 +15,14 @@ class Bank:
sel = Signal() sel = Signal()
comb.append(sel.eq(self.interface.a_i[9:] == Constant(self.address, BV(5)))) comb.append(sel.eq(self.interface.a_i[9:] == Constant(self.address, BV(5))))
nregs = len(self.description) nbits = bits_for(len(self.description)-1)
nbits = bits_for(nregs-1)
# Bus writes # Bus writes
bwcases = [] bwcases = []
for i in range(nregs): for i, reg in enumerate(self.description):
reg = self.description[i]
if reg.raw is None: if reg.raw is None:
bwra = [Constant(i, BV(nbits))] bwra = [Constant(i, BV(nbits))]
nfields = len(reg.fields) for j, field in enumerate(reg.fields):
for j in range(nfields):
field = reg.fields[j]
if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE: if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
bwra.append(field.storage.eq(self.interface.d_i[j])) bwra.append(field.storage.eq(self.interface.d_i[j]))
if len(bwra) > 1: if len(bwra) > 1:
@ -41,14 +37,11 @@ class Bank:
# Bus reads # Bus reads
brcases = [] brcases = []
for i in range(nregs): for i, reg in enumerate(self.description):
reg = self.description[i]
if reg.raw is None: if reg.raw is None:
nfields = len(reg.fields)
brs = [] brs = []
reg_readable = False reg_readable = False
for j in range(nfields): for j, field in enumerate(reg.fields):
field = reg.fields[j]
if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE: if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
brs.append(field.storage) brs.append(field.storage)
reg_readable = True reg_readable = True