soc/interconnect/axi/axi_full: AXIInterconnectShared, AXICrossbar: propagate master bus address width to Interface
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13987659a9
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@ -613,7 +613,8 @@ class AXIInterconnectShared(LiteXModule):
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"""AXI shared interconnect"""
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"""AXI shared interconnect"""
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def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
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def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
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data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
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data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
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shared = AXIInterface(data_width=data_width)
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adr_width = max([m.address_width for m in masters])
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shared = AXIInterface(data_width=data_width, address_width=adr_width)
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self.arbiter = AXIArbiter(masters, shared)
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self.arbiter = AXIArbiter(masters, shared)
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self.decoder = AXIDecoder(shared, slaves)
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self.decoder = AXIDecoder(shared, slaves)
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if timeout_cycles is not None:
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if timeout_cycles is not None:
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@ -626,8 +627,9 @@ class AXICrossbar(LiteXModule):
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"""
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"""
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def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
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def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
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data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
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data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
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adr_width = max([m.address_width for m in masters])
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matches, busses = zip(*slaves)
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matches, busses = zip(*slaves)
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access_m_s = [[AXIInterface(data_width=data_width) for j in slaves] for i in masters] # a[master][slave]
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access_m_s = [[AXIInterface(data_width=data_width, address_width=adr_width) for j in slaves] for i in masters] # a[master][slave]
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access_s_m = list(zip(*access_m_s)) # a[slave][master]
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access_s_m = list(zip(*access_m_s)) # a[slave][master]
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# Decode each master into its access row.
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# Decode each master into its access row.
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for slaves, master in zip(access_m_s, masters):
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for slaves, master in zip(access_m_s, masters):
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