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transport: code SATATransportLayerTX (untested)
This commit is contained in:
Florent Kermarrec
parent
e4c0b4a11f
commit
1aab9a449e
3 changed files with 163 additions and 17 deletions
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@ -48,13 +48,48 @@ def link_layout(dw):
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]
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return EndpointDescription(layout, packetized=True)
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def transport_tx_layout(dw):
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def transport_cmd_tx_layout():
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layout = [
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("d", dw)
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("type", 8),
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("pm_port", 4),
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("a", 1),
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("c", 1),
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("d", 1),
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("i", 1),
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("command", 8),
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("features", 16),
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("lba", 48),
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("device", 8),
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("count", 16),
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("icc", 8),
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("control", 8),
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("dma_buffer_id", 64),
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("dma_buffer_offset", 32),
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("dma_transfer_count", 32),
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]
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return EndpointDescription(layout, packetized=True)
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def transport_rx_layout(dw):
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def transport_cmd_rx_layout():
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layout = [
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("type", 8),
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("pm_port", 4),
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("a", 1),
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("d", 1),
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("i", 1),
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("status", 8),
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("error", 8),
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("lba", 48),
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("device", 8),
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("count", 16),
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("e_status", 8),
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("transfer_count", 16),
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("dma_buffer_id", 64),
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("dma_buffer_offset", 32),
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("dma_transfer_count", 32)
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]
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return EndpointDescription(layout, packetized=True)
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def transport_data_layout(dw):
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layout = [
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("d", dw)
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]
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@ -1,15 +1,125 @@
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from lib.sata.std import *
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from lib.sata.transport.std import *
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def _encode_cmd(obj, layout, signal):
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r = []
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for k, v in sorted(layout.items()):
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start = v.word*32 + v.offset
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end = start + v.width
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r.append(signal[start:end].eq(getattr(obj, k)))
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return r
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class SATATransportLayerTX(Module):
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def __init__(self):
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self.sink = Sink(transport_layout(32))
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def __init__(self, link):
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self.cmd = cmd = Sink(transport_cmd_tx_layout())
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self.data = data = Sink(transport_data_layout(32))
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###
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cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_dma_setup_cmd_len, fis_data_cmd_len)
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encoded_cmd = Signal(cmd_ndwords*32)
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cnt = Signal(max=cmd_ndwords+1)
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clr_cnt = Signal()
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inc_cnt = Signal()
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cmd_len = Signal(flen(cnt))
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cmd_with_data = Signal()
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cmd_send = Signal()
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data_send = Signal()
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cmd_done = Signal()
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data_done = Signal()
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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# FSM
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fsm.act("IDLE",
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clr_cnt.eq(1),
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If(cmd.stb,
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If(cmd.type == fis_types["REG_H2D"],
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NextState("SEND_REG_H2D_CMD")
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).Elif(cmd.type == "DMA_SETUP_CMD",
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NextState("SEND_DMA_SETUP")
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).Elif(cmd.type == "DATA_CMD"),
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NextState("SEND_DATA")
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).Else(
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# XXX: Generate error to command layer?
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cmd.ack.eq(1)
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)
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)
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)
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fsm.act("SEND_REG_H2D_CMD",
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_encode_cmd(self.cmd, fis_reg_h2d_layout, encoded_cmd),
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cmd_len.eq(fis_reg_h2d_cmd_len),
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cmd_send.eq(1)
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If(ack_cmd,
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NextState.eq("ACK")
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)
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)
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fsm.act("SEND_DMA_SETUP_CMD",
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_encode_cmd(self.cmd, fis_dma_setup_layout, encoded_cmd),
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cmd_len.eq(fis_dma_setup_cmd_len),
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cmd_send.eq(1),
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If(ack_cmd,
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NextState.eq("ACK")
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)
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)
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fsm.act("SEND_DATA_CMD",
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_encode_cmd(self.cmd, fis_data_layout, encoded_cmd),
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cmd_len.eq(fis_send_data_cmd_len),
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cmd_width_data.eq(1),
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cmd_send.eq(1),
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If(cmd_done,
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NextState.eq("SEND_DATA")
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)
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)
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fsm.act("SEND_DATA",
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data_send.eq(1),
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If(data_done,
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NextState.eq("ACK")
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)
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)
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fsm.act("ACK",
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cmd.ack.eq(1),
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NextState.eq("IDLE")
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)
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cmd_cases = {}
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for i in range(cmd_ndwords):
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cmd_cases[i] = [link.sink.d.eq(encoded_cmd[32*i:32*(i+1)])]
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self.comb += \
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If(cmd_send,
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link.sink.stb.eq(1),
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link.sink.sop.eq(cnt==0),
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link.sink.eop.eq((cnt==cmd_len) & ~cmd_with_data),
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Case(cnt, cmd_cases),
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inc_cnt.eq(link.sink.ack),
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cmd_done.eq(cnt==cmd_len)
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).Elif(data_send,
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link.sink.stb.eq(data.stb),
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link.sink.sop.eq(0),
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link.sink.eop.eq(data.eop),
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link.sink.d.eq(data.d),
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data.ack.eq(link.sink.ack),
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data_done.eq(data.eop & data.ack)
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)
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self.sync += \
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If(clr_cnt,
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cnt.eq(0)
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).Elif(inc_cnt,
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cnt.eq(cnt+1)
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)
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class SATATransportLayerRX(Module):
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def __init__(self):
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self.sink = Sink(transport_layout(32))
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def __init__(self, link):
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self.cmd = Source(transport_cmd_rx_layout())
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self.data = Source(transport_data_layout(32))
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class SATATransportLayer(Module):
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def __init__(self):
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self.submodules.tx = SATATransportLayerTX()
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self.submodules.rx = SATATransportLayerRX()
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def __init__(self, link):
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self.submodules.tx = SATATransportLayerTX(link)
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self.submodules.rx = SATATransportLayerRX(link)
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@ -13,7 +13,7 @@ class FISField():
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self.offset = offset
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self.width = width
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fis_reg_h2d_len = 5
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fis_reg_h2d_cmd_len = 5
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fis_reg_h2d_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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@ -22,7 +22,7 @@ fis_reg_h2d_layout = {
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"features_lsb": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"device": FISField(1, 24, 0),
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"device": FISField(1, 24, 8),
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"lba_msb": FISField(2, 0, 24),
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"features_msb": FISField(2, 24, 8),
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@ -32,7 +32,7 @@ fis_reg_h2d_layout = {
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"control": FISField(3, 24, 8)
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}
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fis_reg_d2h_len = 5
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fis_reg_d2h_cmd_len = 5
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fis_reg_d2h_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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@ -41,20 +41,20 @@ fis_reg_d2h_layout = {
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"error": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"device": FISField(1, 24, 0),
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"device": FISField(1, 24, 8),
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"lba_msb": FISField(2, 0, 24),
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"count": FISField(3, 0, 16)
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}
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fis_dma_activate_d2h_len = 1
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fis_dma_activate_d2h_cmd_len = 1
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fis_dma_activate_d2h_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4)
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}
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fis_dma_setup_len = 7
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fis_dma_setup_cmd_len = 7
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fis_dma_setup_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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@ -71,6 +71,7 @@ fis_dma_setup_layout = {
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"dma_transfer_count": FISField(4, 0, 32)
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}
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fis_data_cmd_len = 1
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fis_data_layout = {
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"type": FISField(0, 0, 8)
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}
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@ -85,7 +86,7 @@ fis_pio_setup_d2h_layout = {
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"error": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"device": FISField(1, 24, 0),
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"device": FISField(1, 24, 8),
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"lba_msb": FISField(2, 0, 24),
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