soc/cores: add new spi master, remove obsolete one
This commit is contained in:
Florent Kermarrec
parent
f73eb5fe71
commit
1acca39397
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@ -0,0 +1,373 @@
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from itertools import product
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from litex.gen import *
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from litex.soc.interconnect.csr import *
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class SPIClockGen(Module):
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def __init__(self, width):
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self.load = Signal(width)
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self.bias = Signal() # bias this clock phase to longer times
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self.edge = Signal()
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self.clk = Signal(reset=1)
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cnt = Signal.like(self.load)
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bias = Signal()
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zero = Signal()
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self.comb += [
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zero.eq(cnt == 0),
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self.edge.eq(zero & ~bias),
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]
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self.sync += [
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If(zero,
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bias.eq(0),
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).Else(
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cnt.eq(cnt - 1),
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),
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If(self.edge,
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cnt.eq(self.load[1:]),
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bias.eq(self.load[0] & (self.clk ^ self.bias)),
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self.clk.eq(~self.clk),
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)
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]
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class SPIRegister(Module):
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def __init__(self, width):
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self.data = Signal(width)
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self.o = Signal()
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self.i = Signal()
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self.lsb = Signal()
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self.shift = Signal()
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self.sample = Signal()
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self.comb += [
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self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])),
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]
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self.sync += [
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If(self.shift,
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If(self.lsb,
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self.data[:-1].eq(self.data[1:]),
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).Else(
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self.data[1:].eq(self.data[:-1]),
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)
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),
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If(self.sample,
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If(self.lsb,
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self.data[-1].eq(self.i),
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).Else(
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self.data[0].eq(self.i),
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)
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)
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]
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class SPIBitCounter(Module):
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def __init__(self, width):
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self.n_read = Signal(width)
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self.n_write = Signal(width)
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self.read = Signal()
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self.write = Signal()
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self.done = Signal()
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self.comb += [
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self.write.eq(self.n_write != 0),
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self.read.eq(self.n_read != 0),
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self.done.eq(~(self.write | self.read)),
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]
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self.sync += [
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If(self.write,
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self.n_write.eq(self.n_write - 1),
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).Elif(self.read,
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self.n_read.eq(self.n_read - 1),
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)
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]
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class SPIMachine(Module):
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def __init__(self, data_width, clock_width, bits_width):
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ce = CEInserter()
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self.submodules.cg = ce(SPIClockGen(clock_width))
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self.submodules.reg = ce(SPIRegister(data_width))
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self.submodules.bits = ce(SPIBitCounter(bits_width))
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self.div_write = Signal.like(self.cg.load)
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self.div_read = Signal.like(self.cg.load)
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self.clk_phase = Signal()
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self.start = Signal()
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self.cs = Signal()
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self.oe = Signal()
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self.done = Signal()
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# # #
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.start,
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If(self.clk_phase,
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NextState("WAIT"),
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).Else(
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NextState("SETUP"),
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)
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)
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)
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fsm.act("SETUP",
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self.reg.sample.eq(1),
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NextState("HOLD"),
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)
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fsm.act("HOLD",
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If(self.bits.done & ~self.start,
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If(self.clk_phase,
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NextState("IDLE"),
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).Else(
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NextState("WAIT"),
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)
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).Else(
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self.reg.shift.eq(~self.start),
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NextState("SETUP"),
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)
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)
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fsm.act("WAIT",
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If(self.bits.done,
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NextState("IDLE"),
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).Else(
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NextState("SETUP"),
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)
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)
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write0 = Signal()
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self.sync += [
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If(self.cg.edge & self.reg.shift,
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write0.eq(self.bits.write),
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)
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]
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self.comb += [
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self.cg.ce.eq(self.start | self.cs | ~self.cg.edge),
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If(self.bits.write | ~self.bits.read,
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self.cg.load.eq(self.div_write),
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).Else(
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self.cg.load.eq(self.div_read),
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),
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self.cg.bias.eq(self.clk_phase),
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fsm.ce.eq(self.cg.edge),
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self.cs.eq(~fsm.ongoing("IDLE")),
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self.reg.ce.eq(self.cg.edge),
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self.bits.ce.eq(self.cg.edge & self.reg.sample),
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self.done.eq(self.cg.edge & self.bits.done & fsm.ongoing("HOLD")),
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self.oe.eq(write0 | self.bits.write),
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]
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class SPIMasterCore(Module):
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"""SPI Master Core.
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Notes:
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* M = 32 is the data width (maximum write bits, maximum read bits)
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* Every transfer consists of a write_length 0-M bit write followed
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by a read_length 0-M bit read.
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* cs_n is asserted at the beginning and deasserted at the end of the
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transfer if there is no other transfer pending.
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* cs_n handling is agnostic to whether it is one-hot or decoded
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somewhere downstream. If it is decoded, "cs_n all deasserted"
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should be handled accordingly (no slave selected).
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If it is one-hot, asserting multiple slaves should only be attempted
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if miso is either not connected between slaves, or open collector,
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or correctly multiplexed externally.
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* If config.cs_polarity == 0 (cs active low, the default),
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"cs_n all deasserted" means "all cs_n bits high".
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* cs is not mandatory in pads. Framing and chip selection can also
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be handled independently through other means.
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* If there is a miso wire in pads, the input and output can be done
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with two signals (a.k.a. 4-wire SPI), else mosi must be used for
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both output and input (a.k.a. 3-wire SPI) and config.half_duplex
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must to be set when reading data is desired.
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* For 4-wire SPI only the sum of read_length and write_length matters.
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The behavior is the same no matter how the total transfer length is
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divided between the two. For 3-wire SPI, the direction of mosi/miso
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is switched from output to input after write_len cycles, at the
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"shift_out" clk edge corresponding to bit write_length + 1 of the
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transfer.
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* The first bit output on mosi is always the MSB/LSB (depending on
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config.lsb_first) of the miso_data signal, independent of
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xfer.write_len. The last bit input from miso always ends up in
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the LSB/MSB (respectively) of the misoc_data signal, independent of
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read_len.
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* Data output on mosi in 4-wire SPI during the read cycles is what
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is found in the data register at the time.
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Data in the data register outside the least/most (depending
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on config.lsb_first) significant read_length bits is what is
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seen on miso during the write cycles.
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* The SPI data register is double-buffered: Once a transfer has
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started, new write data can be written, queuing a new transfer.
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Transfers submitted this way are chained and executed without
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deasserting cs. Once a transfer completes, the previous transfer's
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read data is available in the data register.
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* Changes to config signal take effect immediately. Changes
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to xfer_* signals are synchronized to the start of a transfer.
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Transaction Sequence:
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* If desired, set the config signal to set up the core.
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* If designed, set the xfer signal to set up lengths and cs_n.
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* Set the miso_data signal (not required for zero-length writes),
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* Set start signal to 1
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* Wait for active and pending signals to be 0.
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* If desired, use the misoc_data signal corresponding to the last
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completed transfer.
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Core IOs:
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config signal:
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1 offline: all pins high-z (reset=1)
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1 active: cs/transfer active (read-only)
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1 pending: transfer pending in intermediate buffer (read-only)
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1 cs_polarity: active level of chip select (reset=0)
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1 clk_polarity: idle level of clk (reset=0)
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1 clk_phase: first edge after cs assertion to sample data on (reset=0)
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(clk_polarity, clk_phase) == (CPOL, CPHA) in Freescale language.
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(0, 0): idle low, output on falling, input on rising
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(0, 1): idle low, output on rising, input on falling
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(1, 0): idle high, output on rising, input on falling
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(1, 1): idle high, output on falling, input on rising
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There is never a clk edge during a cs edge.
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1 lsb_first: LSB is the first bit on the wire (reset=0)
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1 half_duplex: 3-wire SPI, in/out on mosi (reset=0)
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8 undefined
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8 div_write: counter load value to divide this module's clock
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to generate the SPI write clk (reset=0)
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f_clk/f_spi_write == div_write + 2
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8 div_read: ditto for the read clock
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xfer_config signal:
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16 cs: active high bit mask of chip selects to assert (reset=0)
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6 write_len: 0-M bits (reset=0)
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2 undefined
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6 read_len: 0-M bits (reset=0)
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2 undefined
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xfer_mosi/miso_data signal:
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M write/read data (reset=0)
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"""
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def __init__(self, pads):
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self.config = Record([
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("offline", 1),
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("padding0", 2),
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("cs_polarity", 1),
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("clk_polarity", 1),
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("clk_phase", 1),
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("lsb_first", 1),
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("half_duplex", 1),
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("padding1", 8),
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("div_write", 8),
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("div_read", 8),
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])
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self.config.offline.reset = 1
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self.xfer = Record([
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("cs", 16),
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("write_length", 6),
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("padding0", 2),
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("read_length", 6),
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("padding1", 2),
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])
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self.start = Signal()
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self.active = Signal()
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self.pending = Signal()
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self.mosi_data = Signal(32)
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self.miso_data = Signal(32)
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# # #
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self.submodules.machine = machine = SPIMachine(
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data_width=32,
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clock_width=len(self.config.div_read),
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bits_width=len(self.xfer.read_length))
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pending = Signal()
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cs = Signal.like(self.xfer.cs)
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data_read = Signal.like(machine.reg.data)
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data_write = Signal.like(machine.reg.data)
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self.comb += [
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self.miso_data.eq(data_read),
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machine.start.eq(pending & (~machine.cs | machine.done)),
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machine.clk_phase.eq(self.config.clk_phase),
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machine.reg.lsb.eq(self.config.lsb_first),
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machine.div_write.eq(self.config.div_write),
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machine.div_read.eq(self.config.div_read),
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]
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self.sync += [
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If(machine.done,
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data_read.eq(machine.reg.data),
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),
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If(machine.start,
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cs.eq(self.xfer.cs),
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machine.bits.n_write.eq(self.xfer.write_length),
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machine.bits.n_read.eq(self.xfer.read_length),
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machine.reg.data.eq(data_write),
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pending.eq(0),
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),
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If(self.start,
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data_write.eq(self.mosi_data),
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pending.eq(1)
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),
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self.active.eq(machine.cs),
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self.pending.eq(pending),
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]
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# I/O
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if hasattr(pads, "cs_n"):
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cs_n_t = TSTriple(len(pads.cs_n))
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self.specials += cs_n_t.get_tristate(pads.cs_n)
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self.comb += [
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cs_n_t.oe.eq(~self.config.offline),
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cs_n_t.o.eq((cs & Replicate(machine.cs, len(cs))) ^
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Replicate(~self.config.cs_polarity, len(cs))),
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]
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clk_t = TSTriple()
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self.specials += clk_t.get_tristate(pads.clk)
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self.comb += [
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clk_t.oe.eq(~self.config.offline),
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clk_t.o.eq((machine.cg.clk & machine.cs) ^ self.config.clk_polarity),
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]
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mosi_t = TSTriple()
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self.specials += mosi_t.get_tristate(pads.mosi)
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self.comb += [
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mosi_t.oe.eq(~self.config.offline & machine.cs &
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(machine.oe | ~self.config.half_duplex)),
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mosi_t.o.eq(machine.reg.o),
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machine.reg.i.eq(Mux(self.config.half_duplex, mosi_t.i,
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getattr(pads, "miso", mosi_t.i))),
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]
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class SPIMaster(Module, AutoCSR):
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"""SPI Master."""
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def __init__(self, pads, interface="csr"):
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self.submodules.core = core = SPIMasterCore(pads)
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# # #
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if interface == "csr":
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self.config = CSRStorage(32)
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self.xfer = CSRStorage(32)
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self.start = CSR()
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self.active = CSRStatus()
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self.pending = CSRStatus()
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self.mosi_data = CSRStorage(32)
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self.miso_data = CSRStatus(32)
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self.comb += [
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core.config.raw_bits().eq(self.config.storage),
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core.xfer.raw_bits().eq(self.xfer.storage),
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core.start.eq(self.start.re & self.start.r),
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self.active.status.eq(core.active),
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self.pending.status.eq(core.pending),
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core.mosi_data.eq(self.mosi_data.storage),
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self.miso_data.status.eq(core.miso_data)
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]
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else:
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raise NotImplementedError
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@ -1 +0,0 @@
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from litex.soc.cores.spi.core import SPIMaster
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|
|
@ -1,151 +0,0 @@
|
||||||
from litex.gen import *
|
|
||||||
from litex.soc.interconnect.csr import *
|
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|
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||||||
|
|
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class SPIMaster(Module, AutoCSR):
|
|
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def __init__(self, pads, width=24, div=2, cpha=1):
|
|
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self.pads = pads
|
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||||||
|
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||||||
self._ctrl = CSR()
|
|
||||||
self._length = CSRStorage(8)
|
|
||||||
self._status = CSRStatus()
|
|
||||||
if hasattr(pads, "mosi"):
|
|
||||||
self._mosi = CSRStorage(width)
|
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||||||
if hasattr(pads, "miso"):
|
|
||||||
self._miso = CSRStatus(width)
|
|
||||||
|
|
||||||
self.irq = Signal()
|
|
||||||
|
|
||||||
###
|
|
||||||
|
|
||||||
# ctrl
|
|
||||||
start = Signal()
|
|
||||||
length = self._length.storage
|
|
||||||
enable_cs = Signal()
|
|
||||||
enable_shift = Signal()
|
|
||||||
done = Signal()
|
|
||||||
|
|
||||||
self.comb += [
|
|
||||||
start.eq(self._ctrl.re & self._ctrl.r[0]),
|
|
||||||
self._status.status.eq(done)
|
|
||||||
]
|
|
||||||
|
|
||||||
# clk
|
|
||||||
i = Signal(max=div)
|
|
||||||
set_clk = Signal()
|
|
||||||
clr_clk = Signal()
|
|
||||||
self.sync += [
|
|
||||||
If(set_clk,
|
|
||||||
pads.clk.eq(enable_cs)
|
|
||||||
),
|
|
||||||
If(clr_clk,
|
|
||||||
pads.clk.eq(0),
|
|
||||||
i.eq(0)
|
|
||||||
).Else(
|
|
||||||
i.eq(i + 1),
|
|
||||||
)
|
|
||||||
]
|
|
||||||
|
|
||||||
self.comb += [
|
|
||||||
set_clk.eq(i == (div//2-1)),
|
|
||||||
clr_clk.eq(i == (div-1))
|
|
||||||
]
|
|
||||||
|
|
||||||
# fsm
|
|
||||||
cnt = Signal(8)
|
|
||||||
clr_cnt = Signal()
|
|
||||||
inc_cnt = Signal()
|
|
||||||
self.sync += \
|
|
||||||
If(clr_cnt,
|
|
||||||
cnt.eq(0)
|
|
||||||
).Elif(inc_cnt,
|
|
||||||
cnt.eq(cnt+1)
|
|
||||||
)
|
|
||||||
|
|
||||||
fsm = FSM(reset_state="IDLE")
|
|
||||||
self.submodules += fsm
|
|
||||||
fsm.act("IDLE",
|
|
||||||
If(start,
|
|
||||||
NextState("WAIT_CLK")
|
|
||||||
),
|
|
||||||
done.eq(1),
|
|
||||||
clr_cnt.eq(1)
|
|
||||||
)
|
|
||||||
fsm.act("WAIT_CLK",
|
|
||||||
If(clr_clk,
|
|
||||||
NextState("SHIFT")
|
|
||||||
),
|
|
||||||
)
|
|
||||||
fsm.act("SHIFT",
|
|
||||||
If(cnt == length,
|
|
||||||
NextState("END")
|
|
||||||
).Else(
|
|
||||||
inc_cnt.eq(clr_clk),
|
|
||||||
),
|
|
||||||
enable_cs.eq(1),
|
|
||||||
enable_shift.eq(1),
|
|
||||||
)
|
|
||||||
fsm.act("END",
|
|
||||||
If(set_clk,
|
|
||||||
NextState("IDLE")
|
|
||||||
),
|
|
||||||
enable_shift.eq(1),
|
|
||||||
self.irq.eq(1)
|
|
||||||
)
|
|
||||||
|
|
||||||
# miso
|
|
||||||
if hasattr(pads, "miso"):
|
|
||||||
miso = Signal()
|
|
||||||
sr_miso = Signal(width)
|
|
||||||
|
|
||||||
# (cpha = 1: capture on clk falling edge)
|
|
||||||
if cpha:
|
|
||||||
self.sync += \
|
|
||||||
If(enable_shift,
|
|
||||||
If(clr_clk,
|
|
||||||
miso.eq(pads.miso),
|
|
||||||
).Elif(set_clk,
|
|
||||||
sr_miso.eq(Cat(miso, sr_miso[:-1]))
|
|
||||||
)
|
|
||||||
)
|
|
||||||
# (cpha = 0: capture on clk rising edge)
|
|
||||||
else:
|
|
||||||
self.sync += \
|
|
||||||
If(enable_shift,
|
|
||||||
If(set_clk,
|
|
||||||
miso.eq(pads.miso),
|
|
||||||
).Elif(clr_clk,
|
|
||||||
sr_miso.eq(Cat(miso, sr_miso[:-1]))
|
|
||||||
)
|
|
||||||
)
|
|
||||||
self.comb += self._miso.status.eq(sr_miso)
|
|
||||||
|
|
||||||
# mosi
|
|
||||||
if hasattr(pads, "mosi"):
|
|
||||||
sr_mosi = Signal(width)
|
|
||||||
|
|
||||||
# (cpha = 1: propagated on clk rising edge)
|
|
||||||
if cpha:
|
|
||||||
self.sync += \
|
|
||||||
If(start,
|
|
||||||
sr_mosi.eq(self._mosi.storage)
|
|
||||||
).Elif(clr_clk & enable_shift,
|
|
||||||
sr_mosi.eq(Cat(Signal(), sr_mosi[:-1]))
|
|
||||||
).Elif(set_clk,
|
|
||||||
pads.mosi.eq(sr_mosi[-1])
|
|
||||||
)
|
|
||||||
|
|
||||||
# (cpha = 0: propagated on clk falling edge)
|
|
||||||
else:
|
|
||||||
self.sync += [
|
|
||||||
If(start,
|
|
||||||
sr_mosi.eq(self._mosi.storage)
|
|
||||||
).Elif(set_clk & enable_shift,
|
|
||||||
sr_mosi.eq(Cat(Signal(), sr_mosi[:-1]))
|
|
||||||
).Elif(clr_clk,
|
|
||||||
pads.mosi.eq(sr_mosi[-1])
|
|
||||||
)
|
|
||||||
]
|
|
||||||
|
|
||||||
# cs_n
|
|
||||||
self.comb += pads.cs_n.eq(~enable_cs)
|
|
||||||
Loading…
Reference in New Issue