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soc/add_pcie: Make it more flexible to allow disabling DMA tables and passing msis mapping from user design.

This commit is contained in:
Florent Kermarrec 2024-06-25 15:07:05 +02:00
parent 8afa36f24a
commit 1ad0f828bb
1 changed files with 8 additions and 5 deletions
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13
litex/soc/integration/soc.py
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@ -2281,7 +2281,8 @@ class LiteXSoC(SoC):
with_dma_synchronizer = False,
with_dma_monitor = False,
with_dma_status = False,
with_msi = True, msi_type="msi", msi_width=32,
with_dma_table = True,
with_msi = True, msi_type="msi", msi_width=32, msis={},
with_ptm = False,
):
# Imports
@ -2323,7 +2324,7 @@ class LiteXSoC(SoC):
self.add_module(name=f"{name}_msi", module=msi)
if msi_type in ["msi", "msi-multi-vector"]:
self.comb += msi.source.connect(phy.msi)
self.msis = {}
self.msis = msis
# DMAs.
for i in range(ndmas):
@ -2335,16 +2336,18 @@ class LiteXSoC(SoC):
with_synchronizer = with_dma_synchronizer,
with_monitor = with_dma_monitor,
with_status = with_dma_status,
with_table = with_dma_table,
address_width = address_width,
data_width = data_width,
)
self.add_module(name=f"{name}_dma{i}", module=dma)
self.msis[f"{name.upper()}_DMA{i}_WRITER"] = dma.writer.irq
self.msis[f"{name.upper()}_DMA{i}_READER"] = dma.reader.irq
if with_dma_table:
self.msis[f"{name.upper()}_DMA{i}_WRITER"] = dma.writer.irq
self.msis[f"{name.upper()}_DMA{i}_READER"] = dma.reader.irq
self.add_constant("DMA_CHANNELS", ndmas)
self.add_constant("DMA_ADDR_WIDTH", address_width)
# Map/Connect IRQs.
# Map/Connect MSI IRQs.
if with_msi:
for i, (k, v) in enumerate(sorted(self.msis.items())):
self.comb += msi.irqs[i].eq(v)