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test on hardware and first fixes

This commit is contained in:
Florent Kermarrec 2015-02-05 18:59:58 +01:00
parent 8cf9883143
commit 1ae204b7a1
5 changed files with 34 additions and 15 deletions
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7
liteeth/common.py
View File

@ -33,7 +33,6 @@ mac_header = {
"ethernet_type": HField(12, 0, 16)
}
arp_packet_length = 60
arp_hwtype_ethernet = 0x0001
arp_proto_ip = 0x0800
arp_opcode_request = 0x0001
@ -54,9 +53,9 @@ arp_header = {
ipv4_header_len = 20
ipv4_header = {
"version": HField(0, 0, 4),
"ihl": HField(0, 4, 4),
"diff_services": HField(1, 0, 6),
"version": HField(0, 4, 4), # XXX works on hardware but need to fix
"ihl": HField(0, 0, 4), # header encoding/decoding when not aligned
"diff_services": HField(1, 0, 6), # on bytes
"ecn": HField(1, 6, 2),
"total_length": HField(2, 0, 16),
"identification": HField(4, 0, 16),

4
liteeth/core/arp.py
View File

@ -34,7 +34,7 @@ class LiteEthARPTX(Module):
self.submodules += packetizer
source = packetizer.sink
counter = Counter(max=arp_packet_length)
counter = Counter(max=arp_header_len)
self.submodules += counter
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
@ -66,7 +66,7 @@ class LiteEthARPTX(Module):
fsm.act("SEND",
source.stb.eq(1),
source.sop.eq(counter.value == 0),
source.eop.eq(counter.value == arp_packet_length-1),
source.eop.eq(counter.value == arp_header_len-1),
Record.connect(packetizer.source, self.source),
self.source.target_mac.eq(source.target_mac),
self.source.sender_mac.eq(mac_address),

4
liteeth/mac/core/__init__.py
View File

@ -49,8 +49,8 @@ class LiteEthMACCore(Module, AutoCSR):
rx_pipeline += [rx_converter]
# Cross Domain Crossing
tx_cdc = AsyncFIFO(eth_phy_description(dw), 4)
rx_cdc = AsyncFIFO(eth_phy_description(dw), 4)
tx_cdc = AsyncFIFO(eth_phy_description(dw), 8)
rx_cdc = AsyncFIFO(eth_phy_description(dw), 8)
self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})

19
targets/udpip.py
View File

@ -50,7 +50,7 @@ class _CRG(Module):
p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=ClockSignal("eth_tx"), o_O=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
]
@ -127,6 +127,7 @@ class UDPIPBISTGeneratorUnit(Module):
source.eop.eq(counter.value == (self.length-1)),
source.src_port.eq(self.src_port),
source.dst_port.eq(self.dst_port),
source.length.eq(self.length),
source.ip_address.eq(self.ip_address),
source.data.eq(counter.value)
]
@ -169,13 +170,13 @@ class UDPIPSoC(GenSoC, AutoCSR):
}
csr_map.update(GenSoC.csr_map)
def __init__(self, platform):
clk_freq = 166*1000000
clk_freq = 125*1000000
GenSoC.__init__(self, platform, clk_freq)
self.submodules.crg = _CRG(platform)
# Ethernet PHY and UDP/IP
self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.udpip_core = LiteEthUDPIPCore(self.ethphy, convert_ip("192.168.1.40"), 0x10e2d5000000)
self.submodules.udpip_core = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.40"))
# BIST
self.submodules.bist_generator = UDPIPBISTGenerator()
@ -212,6 +213,18 @@ class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
self.udpip_core.mac.core.source.ack,
self.udpip_core.mac.core.source.data,
self.ethphy.sink.stb,
self.ethphy.sink.sop,
self.ethphy.sink.eop,
self.ethphy.sink.ack,
self.ethphy.sink.data,
self.ethphy.source.stb,
self.ethphy.source.sop,
self.ethphy.source.eop,
self.ethphy.source.ack,
self.ethphy.source.data,
self.udpip_core_udp_rx_fsm_state,
self.udpip_core_udp_tx_fsm_state,
self.udpip_core_ip_rx_fsm_state,

15
test/test_udpip.py
View File

@ -1,18 +1,25 @@
from config import *
import time
def convert_ip(s):
ip = 0
for e in s.split("."):
ip = ip << 8
ip += int(e)
return ip
from litescope.host.driver import LiteScopeLADriver
la = LiteScopeLADriver(wb.regs, "la", debug=True)
wb.open()
regs = wb.regs
###
regs.ethphy_crg_reset.write(1)
regs.ethphy_crg_reset.write(0)
time.sleep(5)
#regs.ethphy_crg_reset.write(1)
#regs.ethphy_crg_reset.write(0)
#time.sleep(5)
regs.bist_generator_src_port.write(0x1234)
regs.bist_generator_dst_port.write(0x5678)
regs.bist_generator_ip_address.write(0x12345678)
regs.bist_generator_ip_address.write(convert_ip("192.168.1.10"))
regs.bist_generator_length.write(64)
conditions = {}