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soc/cores/clock: allow ClockSignal to be used for clkin

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This commit is contained in:
Florent Kermarrec 2019-01-16 22:05:52 +01:00
parent 387ee04130
commit 1b23890e0d
1 changed files with 3 additions and 3 deletions
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6
litex/soc/cores/clock.py
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@ -33,7 +33,7 @@ class S7Clocking(Module, AutoCSR):
def register_clkin(self, clkin, freq):
self.clkin = Signal()
if isinstance(clkin, Signal):
if isinstance(clkin, (Signal, ClockSignal)):
self.comb += self.clkin.eq(clkin)
elif isinstance(clkin, Record):
self.specials += DifferentialInput(clkin.p, clkin.n, self.clkin)
@ -224,7 +224,7 @@ class USClocking(Module, AutoCSR):
def register_clkin(self, clkin, freq):
self.clkin = Signal()
if isinstance(clkin, Signal):
if isinstance(clkin, (Signal, ClockSignal)):
self.comb += self.clkin.eq(clkin)
elif isinstance(clkin, Record):
self.specials += DifferentialInput(clkin.p, clkin.n, self.clkin)
@ -413,7 +413,7 @@ class ECP5PLL(Module):
assert freq >= clki_freq_min
assert freq <= clki_freq_max
self.clkin = Signal()
if isinstance(clkin, Signal):
if isinstance(clkin, (Signal, ClockSignal)):
self.comb += self.clkin.eq(clkin)
else:
raise ValueError