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Merge pull request #2143 from FlyGoat/csr-bridge-width
soc/integration/soc: Fix CSRBridge Bus Width conversion
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commit
1b47407aa0
4 changed files with 9 additions and 4 deletions
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@ -1138,13 +1138,14 @@ class SoC(LiteXModule, SoCCoreCompat):
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}[self.bus.standard]
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csr_bridge_name = f"{name}_bridge"
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self.check_if_exists(csr_bridge_name)
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data_width = self.csr.data_width
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csr_bridge = csr_bridge_cls(
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bus_bridge_cls(
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address_width = self.bus.address_width,
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data_width = self.bus.data_width),
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data_width = data_width),
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bus_csr = csr_bus.Interface(
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address_width = self.csr.address_width,
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data_width = self.csr.data_width),
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data_width = data_width),
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register = register)
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self.logger.info("CSR Bridge {} {}.".format(
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colorer(name, color="underline"),
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@ -29,6 +29,8 @@ class AXILite2CSR(LiteXModule):
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self.axi_lite = axi_lite
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self.csr = bus_csr
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assert axi_lite.data_width == bus_csr.data_width
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fsm, comb = axi_lite_to_simple(
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axi_lite = self.axi_lite,
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port_adr = self.csr.adr,
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@ -588,6 +588,8 @@ class Wishbone2CSR(LiteXModule):
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# If no Wishbone bus provided, create it with default parameters.
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self.wishbone = Interface()
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assert self.wishbone.data_width == self.csr.data_width
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# # #
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wishbone_adr_shift = {
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@ -258,8 +258,8 @@ class TestAXILite(unittest.TestCase):
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class DUT(Module):
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def __init__(self):
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self.axi_lite = AXILiteInterface()
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self.csr = csr_bus.Interface()
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self.axi_lite = AXILiteInterface(data_width=32)
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self.csr = csr_bus.Interface(data_width=32)
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self.submodules.axilite2csr = AXILite2CSR(self.axi_lite, self.csr)
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self.errors = 0
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