Instance support
This commit is contained in:
Sebastien Bourdeauducq
parent
fab02f84cb
commit
1b637cea61
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@ -45,6 +45,6 @@ class Divider:
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return f.Fragment(comb, sync)
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d = Divider(32)
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f = d.GetFragment()
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o = verilog.Convert(f, {d.ready_o, d.quotient_o, d.remainder_o}, {d.start_i, d.dividend_i, d.divisor_i})
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frag = d.GetFragment()
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o = verilog.Convert(frag, {d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
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print(o)
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@ -0,0 +1,47 @@
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from migen.fhdl import structure as f
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from migen.fhdl import verilog
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class LM32:
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def __init__(self):
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self.inst = f.Instance("lm32_top",
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[("I_ADR_O", f.BV(32)),
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("I_DAT_O", f.BV(32)),
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("I_SEL_O", f.BV(4)),
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("I_CYC_O", f.BV(1)),
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("I_STB_O", f.BV(1)),
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("I_WE_O", f.BV(1)),
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("I_CTI_O", f.BV(3)),
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("I_LOCK_O", f.BV(1)),
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("I_BTE_O", f.BV(1)),
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("D_ADR_O", f.BV(32)),
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("D_DAT_O", f.BV(32)),
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("D_SEL_O", f.BV(4)),
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("D_CYC_O", f.BV(1)),
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("D_STB_O", f.BV(1)),
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("D_WE_O", f.BV(1)),
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("D_CTI_O", f.BV(3)),
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("D_LOCK_O", f.BV(1)),
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("D_BTE_O", f.BV(1))],
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[("interrupt", f.BV(32)),
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("ext_break", f.BV(1)),
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("I_DAT_I", f.BV(32)),
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("I_ACK_I", f.BV(1)),
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("I_ERR_I", f.BV(1)),
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("I_RTY_I", f.BV(1)),
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("D_DAT_I", f.BV(32)),
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("D_ACK_I", f.BV(1)),
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("D_ERR_I", f.BV(1)),
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("D_RTY_I", f.BV(1))],
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[],
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"clk_i",
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"rst_i",
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"lm32")
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def GetFragment(self):
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return f.Fragment(instances=[self.inst])
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cpus = [LM32() for i in range(4)]
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frag = f.Fragment()
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for cpu in cpus:
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frag += cpu.GetFragment()
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print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
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@ -21,5 +21,5 @@ bank = csrgen.Bank([oreg, ireg])
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f = bank.GetFragment() + inf
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i = bank.interface
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ofield.dev_r.name = "gpio_out"
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v = verilog.Convert(f, {i.d_o, ofield.dev_r}, {i.a_i, i.we_i, i.d_i, gpio_in})
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v = verilog.Convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in})
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print(v)
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@ -70,9 +70,20 @@ def ListTargets(node):
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elif isinstance(node, Case):
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l = list(map(lambda x: ListTargets(x[1]), node.cases))
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return ListTargets(node.default).union(*l)
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elif isinstance(node, Fragment):
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return ListTargets(node.comb) | ListTargets(node.sync)
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else:
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raise TypeError
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def ListInstOuts(i):
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if isinstance(i, Fragment):
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return ListInstOuts(i.instances)
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else:
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l = []
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for x in i:
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l += list(map(lambda x: x[1], list(x.outs.items())))
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return set(l)
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def IsVariable(node):
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if isinstance(node, Signal):
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return node.variable
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@ -150,10 +150,32 @@ class Case:
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#
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class Instance:
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def __init__(self, of, outs=[], ins=[], parameters=[], clkport="", rstport="", name=""):
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self.of = of
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if name:
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self.name = name
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else:
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self.name = of
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self.outs = dict([(x[0], Signal(x[1], self.name + "_" + x[0])) for x in outs])
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self.ins = dict([(x[0], Signal(x[1], self.name + "_" + x[0])) for x in ins])
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self.parameters = parameters
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self.clkport = clkport
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self.rstport = rstport
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def __hash__(self):
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return id(self)
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class Fragment:
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def __init__(self, comb=StatementList(), sync=StatementList()):
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def __init__(self, comb=StatementList(), sync=StatementList(), instances=[]):
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self.comb = _sl(comb)
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self.sync = _sl(sync)
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self.instances = instances
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def __add__(self, other):
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return Fragment(self.comb.l + other.comb.l, self.sync.l + other.sync.l)
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return Fragment(self.comb.l + other.comb.l, self.sync.l + other.sync.l, self.instances + other.instances)
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def __iadd__(self, other):
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self.comb.l += other.comb.l
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self.sync.l += other.sync.l
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self.instances += other.instances
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return self
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@ -2,105 +2,149 @@ from .structure import *
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from .convtools import *
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from functools import partial
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def Convert(f, outs=set(), ins=set(), name="top", clkname="sys_clk", rstname="sys_rst"):
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def _printsig(ns, s):
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if s.bv.signed:
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n = "signed "
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else:
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n = ""
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if s.bv.width > 1:
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n += "[" + str(s.bv.width-1) + ":0] "
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n += ns.GetName(s)
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return n
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def _printexpr(ns, node):
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if isinstance(node, Constant):
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if node.n >= 0:
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return str(node.bv) + str(node.n)
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else:
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return "-" + str(node.bv) + str(-self.n)
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elif isinstance(node, Signal):
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return ns.GetName(node)
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elif isinstance(node, Operator):
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arity = len(node.operands)
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if arity == 1:
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r = self.op + _printexpr(ns, node.operands[0])
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elif arity == 2:
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r = _printexpr(ns, node.operands[0]) + " " + node.op + " " + _printexpr(ns, node.operands[1])
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else:
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raise TypeError
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return "(" + r + ")"
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elif isinstance(node, Slice):
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if node.start + 1 == node.stop:
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sr = "[" + str(node.start) + "]"
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else:
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sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
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return _printexpr(ns, node.value) + sr
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elif isinstance(node, Cat):
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l = list(map(partial(_printexpr, ns), node.l))
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l.reverse()
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return "{" + ", ".join(l) + "}"
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else:
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raise TypeError
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def _printnode(ns, level, comb, node):
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if isinstance(node, Assign):
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if comb or IsVariable(node.l):
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assignment = " = "
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else:
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assignment = " <= "
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return "\t"*level + _printexpr(ns, node.l) + assignment + _printexpr(ns, node.r) + ";\n"
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elif isinstance(node, StatementList):
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return "".join(list(map(partial(_printnode, ns, level, comb), node.l)))
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elif isinstance(node, If):
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r = "\t"*level + "if (" + _printexpr(ns, node.cond) + ") begin\n"
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r += _printnode(ns, level + 1, comb, node.t)
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if node.f.l:
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r += "\t"*level + "end else begin\n"
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r += _printnode(ns, level + 1, comb, node.f)
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r += "\t"*level + "end\n"
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return r
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elif isinstance(node, Case):
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r = "\t"*level + "case (" + _printexpr(ns, node.test) + ")\n"
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for case in node.cases:
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r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n"
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r += _printnode(ns, level + 2, comb, case[1])
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r += "\t"*(level + 1) + "end\n"
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r += "\t"*level + "endcase\n"
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return r
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else:
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raise TypeError
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def _printinstances(ns, i, clk, rst):
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r = ""
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for x in i:
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r += x.of + " "
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if x.parameters:
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r += "#(\n"
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firstp = True
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for p in x.parameters:
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if not firstp:
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r += ",\n"
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firstp = False
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r += "\t." + p[0] + "("
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if isinstance(p[1], int):
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r += str(p[1])
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elif isinstance(p[1], basestring):
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r += "\"" + p[1] + "\""
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else:
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raise TypeError
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r += ")"
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r += "\n) "
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r += ns.GetName(x) + "(\n"
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ports = list(x.ins.items()) + list(x.outs.items())
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if x.clkport:
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ports.append((x.clkport, clk))
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if x.rstport:
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ports.append((x.rstport, rst))
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firstp = True
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for p in ports:
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if not firstp:
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r += ",\n"
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firstp = False
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r += "\t." + p[0] + "(" + ns.GetName(p[1]) + ")"
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if not firstp:
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r += "\n"
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r += ");\n\n"
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return r
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def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst"):
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ns = Namespace()
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clks = Signal(name=clkname)
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rsts = Signal(name=rstname)
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clk = ns.GetName(clks)
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rst = ns.GetName(rsts)
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def printsig(s):
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if s.bv.signed:
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n = "signed "
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else:
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n = ""
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if s.bv.width > 1:
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n += "[" + str(s.bv.width-1) + ":0] "
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n += ns.GetName(s)
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return n
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sigs = ListSignals(f)
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targets = ListTargets(f)
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instouts = ListInstOuts(f)
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def printexpr(node):
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if isinstance(node, Constant):
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if node.n >= 0:
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return str(node.bv) + str(node.n)
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else:
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return "-" + str(node.bv) + str(-self.n)
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elif isinstance(node, Signal):
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return ns.GetName(node)
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elif isinstance(node, Operator):
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arity = len(node.operands)
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if arity == 1:
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r = self.op + printexpr(node.operands[0])
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elif arity == 2:
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r = printexpr(node.operands[0]) + " " + node.op + " " + printexpr(node.operands[1])
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else:
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raise TypeError
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return "(" + r + ")"
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elif isinstance(node, Slice):
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if node.start + 1 == node.stop:
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sr = "[" + str(node.start) + "]"
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else:
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sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
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return printexpr(node.value) + sr
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elif isinstance(node, Cat):
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l = list(map(printexpr, node.l))
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l.reverse()
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return "{" + ", ".join(l) + "}"
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else:
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raise TypeError
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def printnode(level, comb, node):
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if isinstance(node, Assign):
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if comb or IsVariable(node.l):
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assignment = " = "
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else:
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assignment = " <= "
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return "\t"*level + printexpr(node.l) + assignment + printexpr(node.r) + ";\n"
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elif isinstance(node, StatementList):
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return "".join(list(map(partial(printnode, level, comb), node.l)))
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elif isinstance(node, If):
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r = "\t"*level + "if (" + printexpr(node.cond) + ") begin\n"
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r += printnode(level + 1, comb, node.t)
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if node.f.l:
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r += "\t"*level + "end else begin\n"
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r += printnode(level + 1, comb, node.f)
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r += "\t"*level + "end\n"
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return r
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elif isinstance(node, Case):
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r = "\t"*level + "case (" + printexpr(node.test) + ")\n"
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for case in node.cases:
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r += "\t"*(level + 1) + printexpr(case[0]) + ": begin\n"
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r += printnode(level + 2, comb, case[1])
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r += "\t"*(level + 1) + "end\n"
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r += "\t"*level + "endcase\n"
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return r
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else:
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raise TypeError
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r = "/* Autogenerated by Migen */\n"
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r = "/* Machine-generated using Migen */\n"
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r += "module " + name + "(\n"
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r += "\tinput " + clk + ",\n"
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r += "\tinput " + rst
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if ins:
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r += ",\n\tinput " + ",\n\tinput ".join(map(printsig, ins))
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if outs:
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r += ",\n\toutput reg " + ",\n\toutput reg ".join(map(printsig, outs))
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r += "\tinput " + ns.GetName(clks) + ",\n"
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r += "\tinput " + ns.GetName(rsts)
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for sig in ios:
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if sig in targets:
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r += ",\n\toutput reg " + _printsig(ns, sig)
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elif sig in instouts:
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r += ",\n\toutput " + _printsig(ns, sig)
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else:
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r += ",\n\tinput " + _printsig(ns, sig)
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r += "\n);\n\n"
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sigs = ListSignals(f).difference(ins, outs)
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for sig in sigs:
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r += "reg " + printsig(sig) + ";\n"
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for sig in sigs - ios:
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if sig in instouts:
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r += "wire " + _printsig(ns, sig) + ";\n"
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else:
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r += "reg " + _printsig(ns, sig) + ";\n"
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r += "\n"
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if f.comb.l:
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r += "always @(*) begin\n"
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r += printnode(1, True, f.comb)
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r += _printnode(ns, 1, True, f.comb)
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r += "end\n\n"
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if f.sync.l:
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r += "always @(posedge " + clk + ") begin\n"
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r += printnode(1, False, InsertReset(rsts, f.sync))
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r += "always @(posedge " + ns.GetName(clks) + ") begin\n"
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r += _printnode(ns, 1, False, InsertReset(rsts, f.sync))
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r += "end\n\n"
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r += _printinstances(ns, f.instances, clks, rsts)
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r += "endmodule\n"
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