targets/simple: use new generic DifferentialInput
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@ -1,5 +1,6 @@
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from migen.fhdl.std import *
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus import wishbone
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from migen.genlib.io import DifferentialInput
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from misoclib.soc import SoC, mem_decoder
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from misoclib.soc import SoC, mem_decoder
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from misoclib.com.liteeth.phy import LiteEthPHY
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from misoclib.com.liteeth.phy import LiteEthPHY
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@ -29,12 +30,7 @@ class BaseSoC(SoC):
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clk_in = platform.request(platform.default_clk_name)
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clk_in = platform.request(platform.default_clk_name)
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clk_crg = Signal()
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clk_crg = Signal()
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if hasattr(clk_in, "p"):
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if hasattr(clk_in, "p"):
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from mibuild.xilinx.vivado import XilinxVivadoPlatform
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self.specials += DifferentialInput(clk_in.p, clk_in.n, clk_crg)
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from mibuild.xilinx.ise import XilinxISEPlatform
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if isinstance(platform, (XilinxISEPlatform, XilinxVivadoPlatform)):
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self.specials += Instance("IBUFDS", i_I=clk_in.p, i_IB=clk_in.n, o_O=clk_crg)
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else:
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raise NotImplementedError
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else:
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else:
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self.comb += clk_crg.eq(clk_in)
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self.comb += clk_crg.eq(clk_in)
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self.submodules.crg = _CRG(clk_crg)
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self.submodules.crg = _CRG(clk_crg)
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