vexrisc_smp: fix DMA bus address_width calculation
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@ -337,7 +337,7 @@ class VexRiscvSMP(CPU):
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# DMA.
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# DMA.
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if VexRiscvSMP.coherent_dma:
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if VexRiscvSMP.coherent_dma:
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self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width)
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self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width, address_width=32)
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dma_bus_stall = Signal()
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dma_bus_stall = Signal()
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dma_bus_inhibit = Signal()
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dma_bus_inhibit = Signal()
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self.cpu_params.update(
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self.cpu_params.update(
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