Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vexrisc_smp: fix DMA bus address_width calculation

This commit is contained in:
Andrew Dennison 2023-09-02 11:44:09 +10:00
parent 48ab96fd43
commit 1bb4d299a6
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/cores/cpu/vexriscv_smp/core.py
View File

@ -337,7 +337,7 @@ class VexRiscvSMP(CPU):
# DMA. # DMA.
if VexRiscvSMP.coherent_dma: if VexRiscvSMP.coherent_dma:
self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width) self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width, address_width=32)
dma_bus_stall = Signal() dma_bus_stall = Signal()
dma_bus_inhibit = Signal() dma_bus_inhibit = Signal()
self.cpu_params.update( self.cpu_params.update(