vexrisc_smp: fix DMA bus address_width calculation

2023-09-02 11:44:09 +10:00 · 2023-09-02 11:44:09 +10:00 · 1bb4d299a6
parent 48ab96fd43
commit 1bb4d299a6
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@ -337,7 +337,7 @@ class VexRiscvSMP(CPU):

        # DMA.
        if VexRiscvSMP.coherent_dma:
-            self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width)
+            self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width, address_width=32)
            dma_bus_stall   = Signal()
            dma_bus_inhibit = Signal()
            self.cpu_params.update(