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migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things
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3 changed files with 13 additions and 11 deletions
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@ -4,7 +4,8 @@ from itertools import combinations
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Fragment
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from migen.fhdl.specials import Special
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from migen.fhdl.tools import flat_iteration, rename_clock_domain
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from migen.fhdl.tools import rename_clock_domain
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from migen.util.misc import flat_iteration
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class FinalizeError(Exception):
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pass
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@ -1,17 +1,8 @@
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import collections
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Slice, _Assign
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from migen.fhdl.visit import NodeVisitor, NodeTransformer
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from migen.fhdl.size import value_bits_sign
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def flat_iteration(l):
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for element in l:
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if isinstance(element, collections.Iterable):
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for element2 in flat_iteration(element):
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yield element2
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else:
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yield element
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from migen.util.misc import flat_iteration
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class _SignalLister(NodeVisitor):
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def __init__(self):
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@ -1,3 +1,13 @@
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import collections
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def flat_iteration(l):
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for element in l:
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if isinstance(element, collections.Iterable):
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for element2 in flat_iteration(element):
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yield element2
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else:
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yield element
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def xdir(obj, return_values=False):
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for attr in dir(obj):
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if attr[:2] != "__" and attr[-2:] != "__":
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