command: add robustness and simplify RX path
This commit is contained in:
Florent Kermarrec
parent
aed1064465
commit
1c03f72252
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@ -107,7 +107,7 @@ class SATABIST(Module, AutoCSR):
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def __init__(self, sata_con):
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self._start = CSR()
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self._start_sector = CSRStorage(48)
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self._count = CSRStorage(4)
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self._count = CSRStorage(16)
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self._write_only = CSRStorage()
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self._read_only = CSRStorage()
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@ -135,16 +135,16 @@ class SATACommandRX(Module):
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If(from_tx.write,
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NextState("WAIT_WRITE_ACTIVATE_OR_REG_D2H")
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).Elif(from_tx.read,
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NextState("WAIT_READ_DATA")
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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)
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)
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fsm.act("WAIT_WRITE_ACTIVATE_OR_REG_D2H",
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# XXX: use status and error fields of REG_D2H
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transport.source.ack.eq(1),
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If(transport.source.stb,
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If(test_type("DMA_ACTIVATE_D2H"),
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dma_activate.eq(1),
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).Elif(test_type("REG_D2H"),
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# XXX: use status and error fields of REG_D2H
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NextState("PRESENT_WRITE_RESPONSE")
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)
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)
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@ -159,12 +159,15 @@ class SATACommandRX(Module):
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NextState("IDLE")
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)
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)
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fsm.act("WAIT_READ_DATA",
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fsm.act("WAIT_READ_DATA_OR_REG_D2H",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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transport.source.ack.eq(0),
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If(test_type("DATA"),
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NextState("PRESENT_READ_DATA")
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).Elif(test_type("REG_D2H"),
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# XXX: use status and error fields of REG_D2H
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NextState("PRESENT_READ_RESPONSE")
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)
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)
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)
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@ -178,7 +181,7 @@ class SATACommandRX(Module):
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self.dwords_counter.ce.eq(~read_done),
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If(data_buffer.sink.eop,
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If(read_done,
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NextState("WAIT_READ_REG_D2H")
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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).Else(
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NextState("PRESENT_READ_RESPONSE")
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)
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@ -187,20 +190,11 @@ class SATACommandRX(Module):
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)
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read_error = Signal()
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self.sync += \
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If(fsm.ongoing("WAIT_READ_DATA"),
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If(fsm.before_entering("PRESENT_READ_DATA"),
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read_error.eq(1)
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).Elif(transport.source.stb & transport.source.ack & transport.source.eop,
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read_error.eq(transport.source.error)
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)
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fsm.act("WAIT_READ_REG_D2H",
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# XXX: use status and error fields of REG_D2H
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transport.source.ack.eq(1),
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If(transport.source.stb,
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If(test_type("REG_D2H"),
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NextState("PRESENT_READ_RESPONSE")
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)
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)
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)
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fsm.act("PRESENT_READ_RESPONSE",
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cmd_buffer.sink.stb.eq(1),
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cmd_buffer.sink.read.eq(1),
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@ -214,57 +208,47 @@ class SATACommandRX(Module):
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If(read_done,
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NextState("IDLE")
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).Else(
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NextState("WAIT_READ_DATA")
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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)
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)
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)
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self.out_fsm = out_fsm = FSM(reset_state="IDLE")
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out_fsm.act("IDLE",
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If(cmd_buffer.source.stb & cmd_buffer.source.write,
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NextState("PRESENT_WRITE_RESPONSE"),
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).Elif(cmd_buffer.source.stb & (cmd_buffer.source.read),
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If(cmd_buffer.source.success,
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NextState("PRESENT_READ_RESPONSE_SUCCESS"),
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If(cmd_buffer.source.stb,
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If(cmd_buffer.source.read & cmd_buffer.source.success,
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NextState("PRESENT_RESPONSE_WITH_DATA"),
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).Else(
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NextState("PRESENT_READ_RESPONSE_FAILED"),
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NextState("PRESENT_RESPONSE_WITHOUT_DATA"),
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)
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)
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)
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# XXX try to merge PRESENT_XXX states
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out_fsm.act("PRESENT_WRITE_RESPONSE",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.write.eq(1),
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self.comb += [
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source.write.eq(cmd_buffer.source.write),
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source.read.eq(cmd_buffer.source.read),
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source.last.eq(cmd_buffer.source.last),
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source.success.eq(cmd_buffer.source.success),
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If(source.stb & source.ack,
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cmd_buffer.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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out_fsm.act("PRESENT_READ_RESPONSE_SUCCESS",
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source.failed.eq(cmd_buffer.source.success),
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]
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out_fsm.act("PRESENT_RESPONSE_WITH_DATA",
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source.stb.eq(data_buffer.source.stb),
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source.read.eq(cmd_buffer.source.read),
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source.success.eq(1),
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source.last.eq(cmd_buffer.source.last),
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source.sop.eq(data_buffer.source.sop),
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source.eop.eq(data_buffer.source.eop),
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source.data.eq(data_buffer.source.data),
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data_buffer.source.ack.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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cmd_buffer.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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out_fsm.act("PRESENT_READ_RESPONSE_FAILED",
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out_fsm.act("PRESENT_RESPONSE_WITHOUT_DATA",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(cmd_buffer.source.read),
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source.last.eq(cmd_buffer.source.last),
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source.failed.eq(1),
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If(source.stb & source.ack,
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cmd_buffer.source.ack.eq(1),
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NextState("IDLE")
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