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targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics
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1 changed files with 2 additions and 2 deletions
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@ -84,14 +84,14 @@ class BaseSoC(SDRAMSoC):
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self.submodules.crg = _CRG(platform)
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if not self.with_main_ram:
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sdram_module = MT8JTF12864(self.clk_freq)
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sdram_modules = MT8JTF12864(self.clk_freq)
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sdram_controller_settings = sdram.ControllerSettings(
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req_queue_size=8,
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read_time=32,
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write_time=16
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)
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self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
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self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
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self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings,
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sdram_controller_settings)
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spiflash_pads = platform.request("spiflash")
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