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k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)

This commit is contained in:
Florent Kermarrec 2014-08-14 16:33:59 +02:00 committed by Sebastien Bourdeauducq
parent acbba37f5f
commit 1c381acc6f
1 changed files with 4 additions and 4 deletions
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8
misoclib/sdramphy/k7ddrphy.py
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@ -22,7 +22,7 @@ class K7DDRPHY(Module):
wrcmdphase=0, wrcmdphase=0,
cl=8, cl=8,
cwl=6, cwl=6,
read_latency=8, read_latency=6,
write_latency=2 write_latency=2
) )
@ -211,12 +211,12 @@ class K7DDRPHY(Module):
) )
] ]
# total read latency = 8: # total read latency = 6:
# 2 cycles through OSERDESE2 # 2 cycles through OSERDESE2
# 4 cycles CAS # 2 cycles CAS
# 2 cycles through ISERDESE2 # 2 cycles through ISERDESE2
rddata_en = self.dfi.phases[self.phy_settings.rdphase].rddata_en rddata_en = self.dfi.phases[self.phy_settings.rdphase].rddata_en
for i in range(7): for i in range(5):
n_rddata_en = Signal() n_rddata_en = Signal()
self.sync += n_rddata_en.eq(rddata_en) self.sync += n_rddata_en.eq(rddata_en)
rddata_en = n_rddata_en rddata_en = n_rddata_en