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cores/clocks/lattice_ecp5: Allow manual placement

This commit is contained in:
Marcus Comstedt 2022-07-13 11:10:54 +02:00
parent 2b5a942427
commit 1c51feb21d
1 changed files with 4 additions and 1 deletions
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5
litex/soc/cores/clock/lattice_ecp5.py
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@ -22,7 +22,7 @@ class ECP5PLL(Module):
vco_freq_range = ( 400e6, 800e6)
pfd_freq_range = ( 10e6, 400e6)
def __init__(self):
def __init__(self, bel=None):
self.logger = logging.getLogger("ECP5PLL")
self.logger.info("Creating ECP5PLL.")
self.reset = Signal()
@ -35,6 +35,7 @@ class ECP5PLL(Module):
self.clkouts = {}
self.config = {}
self.params = {}
self.bel = bel
def register_clkin(self, clkin, freq):
(clki_freq_min, clki_freq_max) = self.clki_freq_range
@ -164,6 +165,8 @@ class ECP5PLL(Module):
self.params[f"o_CLKO{n_to_l[n]}"] = clk
if f > 0: # i.e. not a feedback-only clock
self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))
if self.bel:
self.params["attr"].append(("BEL", self.bel))
self.specials += Instance("EHXPLLL", **self.params)
# Lattice / ECP5 Dynamic Delay ---------------------------------------------------------------------