cores/clocks/lattice_ecp5: Allow manual placement
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2b5a942427
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1c51feb21d
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@ -22,7 +22,7 @@ class ECP5PLL(Module):
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vco_freq_range = ( 400e6, 800e6)
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vco_freq_range = ( 400e6, 800e6)
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pfd_freq_range = ( 10e6, 400e6)
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pfd_freq_range = ( 10e6, 400e6)
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def __init__(self):
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def __init__(self, bel=None):
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self.logger = logging.getLogger("ECP5PLL")
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self.logger = logging.getLogger("ECP5PLL")
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self.logger.info("Creating ECP5PLL.")
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self.logger.info("Creating ECP5PLL.")
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self.reset = Signal()
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self.reset = Signal()
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@ -35,6 +35,7 @@ class ECP5PLL(Module):
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self.clkouts = {}
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self.clkouts = {}
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self.config = {}
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self.config = {}
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self.params = {}
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self.params = {}
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self.bel = bel
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def register_clkin(self, clkin, freq):
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def register_clkin(self, clkin, freq):
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(clki_freq_min, clki_freq_max) = self.clki_freq_range
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(clki_freq_min, clki_freq_max) = self.clki_freq_range
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@ -164,6 +165,8 @@ class ECP5PLL(Module):
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self.params[f"o_CLKO{n_to_l[n]}"] = clk
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self.params[f"o_CLKO{n_to_l[n]}"] = clk
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if f > 0: # i.e. not a feedback-only clock
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if f > 0: # i.e. not a feedback-only clock
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self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))
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self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))
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if self.bel:
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self.params["attr"].append(("BEL", self.bel))
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self.specials += Instance("EHXPLLL", **self.params)
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self.specials += Instance("EHXPLLL", **self.params)
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# Lattice / ECP5 Dynamic Delay ---------------------------------------------------------------------
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# Lattice / ECP5 Dynamic Delay ---------------------------------------------------------------------
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