Merge pull request #580 from Dolu1990/patch-2

Improve verilator compilation speed
2020-07-01 08:37:03 +02:00 · 2020-07-01 08:37:03 +02:00 · 1c631ceeee
parent 949a8e73c2 b455a81678
commit 1c631ceeee
1 changed files with 3 additions and 0 deletions
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@ -45,6 +45,9 @@ sim: $(OBJS_SIM) | mkdir
 		$(if $(TRACE_FST), --trace-fst,) \
 		$(if $(COVERAGE), --coverage,) \
 		--unroll-count 256 \
+		--output-split 5000 \
+		--output-split-cfuncs 500 \
+		--output-split-ctrace 500 \
 		$(INC_DIR) \
 		-Wno-BLKANDNBLK \
 		-Wno-WIDTH