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integration/soc: mode litedram imports to add_sdram, remove some separators.

This commit is contained in:
Florent Kermarrec 2020-03-01 18:58:55 +01:00
parent 54fb3a61cd
commit 1c74143a39
1 changed files with 11 additions and 10 deletions
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21
litex/soc/integration/soc.py
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@ -20,10 +20,6 @@ from litex.soc.interconnect import wishbone
from litex.soc.interconnect import wishbone2csr from litex.soc.interconnect import wishbone2csr
from litex.soc.interconnect import axi from litex.soc.interconnect import axi
from litedram.core import LiteDRAMCore
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
from litedram.frontend.axi import LiteDRAMAXI2Native
# TODO: # TODO:
# - replace raise with exit on logging error. # - replace raise with exit on logging error.
# - cleanup SoCCSRRegion # - cleanup SoCCSRRegion
@ -929,7 +925,12 @@ class LiteXSoC(SoC):
l2_cache_full_memory_we = True, l2_cache_full_memory_we = True,
**kwargs): **kwargs):
# LiteDRAM core ---------------------------------------------------------------------------- # Imports
from litedram.core import LiteDRAMCore
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
from litedram.frontend.axi import LiteDRAMAXI2Native
# LiteDRAM core
self.submodules.sdram = LiteDRAMCore( self.submodules.sdram = LiteDRAMCore(
phy = phy, phy = phy,
geom_settings = module.geom_settings, geom_settings = module.geom_settings,
@ -938,11 +939,11 @@ class LiteXSoC(SoC):
**kwargs) **kwargs)
self.csr.add("sdram") self.csr.add("sdram")
# LiteDRAM port ---------------------------------------------------------------------------- # LiteDRAM port
port = self.sdram.crossbar.get_port() port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2 port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
# SDRAM size ------------------------------------------------------------------------------- # SDRAM size
sdram_size = 2**(module.geom_settings.bankbits + sdram_size = 2**(module.geom_settings.bankbits +
module.geom_settings.rowbits + module.geom_settings.rowbits +
module.geom_settings.colbits)*phy.settings.databits//8 module.geom_settings.colbits)*phy.settings.databits//8
@ -981,11 +982,11 @@ class LiteXSoC(SoC):
base_address = origin) base_address = origin)
self.submodules += wishbone.Converter(mem_wb, litedram_wb) self.submodules += wishbone.Converter(mem_wb, litedram_wb)
elif self.with_wishbone: elif self.with_wishbone:
# Wishbone Slave SDRAM interface ------------------------------------------------------- # Wishbone Slave SDRAM interface
wb_sdram = wishbone.Interface() wb_sdram = wishbone.Interface()
self.bus.add_slave("main_ram", wb_sdram) self.bus.add_slave("main_ram", wb_sdram)
# L2 Cache ----------------------------------------------------------------------------- # L2 Cache
if l2_cache_size != 0: if l2_cache_size != 0:
# Insert L2 cache inbetween Wishbone bus and LiteDRAM # Insert L2 cache inbetween Wishbone bus and LiteDRAM
l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
@ -1005,6 +1006,6 @@ class LiteXSoC(SoC):
self.submodules += wishbone.Converter(wb_sdram, litedram_wb) self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
self.add_config("L2_SIZE", l2_cache_size) self.add_config("L2_SIZE", l2_cache_size)
# Wishbone Slave <--> LiteDRAM bridge -------------------------------------------------- # Wishbone Slave <--> LiteDRAM bridge
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port, self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
base_address = self.bus.regions["main_ram"].origin) base_address = self.bus.regions["main_ram"].origin)