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Merge pull request #1161 from stffrdhrn/or1k-marocchino
marocchino: Add initial support for new OpenRISC core
This commit is contained in:
enjoy-digital
GitHub
commit
1c82b20fcb
8 changed files with 1384 additions and 0 deletions
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@ -75,6 +75,7 @@ from litex.soc.cores.cpu.lm32 import LM32
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# OpenRisc
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from litex.soc.cores.cpu.mor1kx import MOR1KX
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from litex.soc.cores.cpu.marocchino import Marocchino
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# OpenPower
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from litex.soc.cores.cpu.microwatt import Microwatt
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@ -114,6 +115,7 @@ CPUS = {
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# OpenRisc
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"mor1kx" : MOR1KX,
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"marocchino" : Marocchino,
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# OpenPower
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"microwatt" : Microwatt,
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1
litex/soc/cores/cpu/marocchino/__init__.py
Normal file
1
litex/soc/cores/cpu/marocchino/__init__.py
Normal file
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@ -0,0 +1 @@
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from litex.soc.cores.cpu.marocchino.core import Marocchino
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5
litex/soc/cores/cpu/marocchino/boot-helper.S
Normal file
5
litex/soc/cores/cpu/marocchino/boot-helper.S
Normal file
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@ -0,0 +1,5 @@
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.section .text, "ax", @progbits
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.global boot_helper
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boot_helper:
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l.jr r6
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l.nop
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171
litex/soc/cores/cpu/marocchino/core.py
Normal file
171
litex/soc/cores/cpu/marocchino/core.py
Normal file
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@ -0,0 +1,171 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018-2017 Tim 'mithro' Ansell <me@mith.ro>
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# Copyright (c) 2019 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = ["standard", "linux", "linux+smp"]
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# Mor1kx -------------------------------------------------------------------------------------------
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class Marocchino(CPU):
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family = "or1k"
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name = "marocchino"
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human_name = "Marocchino"
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variants = CPU_VARIANTS
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data_width = 32
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endianness = "big"
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gcc_triple = ("or1k-elf", "or1k-linux")
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clang_triple = "or1k-linux"
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linker_output_format = "elf32-or1k"
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nop = "l.nop"
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io_regions = {0x80000000: 0x80000000} # Origin, Length.
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# Memory Mapping for Linux variant.
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@property
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def mem_map_linux(self):
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# Mainline Linux OpenRISC arch code requires Linux kernel to be loaded at the physical
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# address of 0x0. As we are running Linux from the MAIN_RAM region - move it to satisfy
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# that requirement.
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return {
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"main_ram" : 0x00000000,
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"rom" : 0x10000000,
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"sram" : 0x50000000,
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"csr" : 0xe0000000,
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}
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# GCC Flags.
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@property
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def gcc_flags(self):
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flags = "-mhard-mul "
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flags += "-mhard-div "
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flags += "-mcmov "
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flags += "-D__mor1kx__ "
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if "linux" in self.variant:
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flags += "-mror "
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flags += "-msext "
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return flags
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# Clang Flags.
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@property
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def clang_flags(self):
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flags = "-mhard-mul "
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flags += "-mhard-div "
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flags += "-mffl1 "
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flags += "-maddc "
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flags += "-D__mor1kx__ "
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return flags
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# Reserved Interrupts.
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@property
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def reserved_interrupts(self):
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return {"nmi": 0}
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.interrupt = Signal(32)
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self.ibus = ibus = wishbone.Interface()
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self.dbus = dbus = wishbone.Interface()
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self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
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self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
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# # #
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# CPU parameters.
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cpu_args = dict(
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p_OPTION_ICACHE_BLOCK_WIDTH = 4,
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p_OPTION_ICACHE_SET_WIDTH = 8,
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p_OPTION_ICACHE_WAYS = 1,
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p_OPTION_ICACHE_LIMIT_WIDTH = 31,
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p_OPTION_DCACHE_BLOCK_WIDTH = 4,
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p_OPTION_DCACHE_SET_WIDTH = 8,
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p_OPTION_DCACHE_WAYS = 1,
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p_OPTION_DCACHE_LIMIT_WIDTH = 31,
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p_OPTION_PIC_TRIGGER = "LEVEL",
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)
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# SMP parameters.
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if "smp" in variant:
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cpu_args.update(p_OPTION_RF_NUM_SHADOW_GPR=1)
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# Linux parameters
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if "linux" in variant:
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# Linux variant requires specific Memory Mapping.
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self.mem_map = self.mem_map_linux
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self.cpu_params = dict(
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**cpu_args,
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# Clk / Rst.
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i_wb_clk = ClockSignal("sys"),
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i_wb_rst = ResetSignal("sys") | self.reset,
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i_cpu_clk = ClockSignal("sys"),
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i_cpu_rst = ResetSignal("sys") | self.reset,
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# IBus.
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o_iwbm_adr_o = Cat(Signal(2), ibus.adr),
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o_iwbm_stb_o = ibus.stb,
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o_iwbm_cyc_o = ibus.cyc,
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o_iwbm_sel_o = ibus.sel,
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o_iwbm_we_o = ibus.we,
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o_iwbm_cti_o = ibus.cti,
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o_iwbm_bte_o = ibus.bte,
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o_iwbm_dat_o = ibus.dat_w,
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i_iwbm_err_i = ibus.err,
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i_iwbm_ack_i = ibus.ack,
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i_iwbm_dat_i = ibus.dat_r,
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i_iwbm_rty_i = 0,
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# DBus.
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o_dwbm_adr_o = Cat(Signal(2), dbus.adr),
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o_dwbm_stb_o = dbus.stb,
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o_dwbm_cyc_o = dbus.cyc,
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o_dwbm_sel_o = dbus.sel,
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o_dwbm_we_o = dbus.we,
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o_dwbm_cti_o = dbus.cti,
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o_dwbm_bte_o = dbus.bte,
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o_dwbm_dat_o = dbus.dat_w,
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i_dwbm_ack_i = dbus.ack,
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i_dwbm_err_i = dbus.err,
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i_dwbm_dat_i = dbus.dat_r,
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i_dwbm_rty_i = 0,
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# IRQ.
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i_irq_i=self.interrupt,
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)
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# Add Verilog sources.
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self.add_sources(platform)
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def set_reset_address(self, reset_address):
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self.reset_address = reset_address
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self.cpu_params.update(p_OPTION_RESET_PC=reset_address)
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@staticmethod
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def add_sources(platform):
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vdir = os.path.join(
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get_data_mod("cpu", "marocchino").data_location,
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"rtl", "verilog")
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platform.add_source_dir(vdir)
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platform.add_verilog_include_path(vdir)
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("or1k_marocchino_top", **self.cpu_params)
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394
litex/soc/cores/cpu/marocchino/crt0.S
Normal file
394
litex/soc/cores/cpu/marocchino/crt0.S
Normal file
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@ -0,0 +1,394 @@
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/*
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* (C) Copyright 2012, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <spr-defs.h>
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/*
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* OR1K Architecture has a 128 byte "red zone" after the stack that can not be
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* touched by exception handlers. GCC uses this red zone for locals and
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* temps without needing to change the stack pointer.
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*/
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#define OR1K_RED_ZONE_SIZE 128
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/*
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* We need 4 bytes (32 bits) * 32 registers space on the stack to save all the
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* registers.
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*/
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#define EXCEPTION_STACK_SIZE ((4*32) + OR1K_RED_ZONE_SIZE)
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#define HANDLE_EXCEPTION ; \
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l.addi r1, r1, -EXCEPTION_STACK_SIZE ; \
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l.sw 0x1c(r1), r9 ; \
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l.jal _exception_handler ; \
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l.nop ; \
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l.lwz r9, 0x1c(r1) ; \
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l.addi r1, r1, EXCEPTION_STACK_SIZE ; \
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l.rfe ; \
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l.nop
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.section .text, "ax", @progbits
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.global _start
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_start:
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_reset_handler:
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l.movhi r0, 0
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l.movhi r1, 0
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l.movhi r2, 0
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l.movhi r3, 0
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l.movhi r4, 0
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l.movhi r5, 0
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l.movhi r6, 0
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l.movhi r7, 0
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l.movhi r8, 0
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l.movhi r9, 0
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l.movhi r10, 0
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l.movhi r11, 0
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l.movhi r12, 0
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l.movhi r13, 0
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l.movhi r14, 0
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l.movhi r15, 0
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l.movhi r16, 0
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l.movhi r17, 0
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l.movhi r18, 0
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l.movhi r19, 0
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l.movhi r20, 0
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l.movhi r21, 0
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l.movhi r22, 0
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l.movhi r23, 0
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l.movhi r24, 0
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l.movhi r25, 0
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l.movhi r26, 0
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l.movhi r27, 0
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l.movhi r28, 0
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l.movhi r29, 0
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l.movhi r30, 0
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l.movhi r31, 0
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l.ori r21, r0, SPR_SR_SM
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l.mtspr r0, r21, SPR_SR
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l.movhi r21, hi(_reset_handler)
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l.ori r21, r21, lo(_reset_handler)
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l.mtspr r0, r21, SPR_EVBAR
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/* enable caches */
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l.jal _cache_init
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l.nop
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l.j _crt0
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l.nop
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/* bus error */
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.org 0x200
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HANDLE_EXCEPTION
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/* data page fault */
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.org 0x300
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HANDLE_EXCEPTION
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/* instruction page fault */
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.org 0x400
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HANDLE_EXCEPTION
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/* tick timer */
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.org 0x500
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HANDLE_EXCEPTION
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/* alignment */
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.org 0x600
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HANDLE_EXCEPTION
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/* illegal instruction */
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.org 0x700
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HANDLE_EXCEPTION
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/* external interrupt */
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.org 0x800
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HANDLE_EXCEPTION
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/* D-TLB miss */
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.org 0x900
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HANDLE_EXCEPTION
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/* I-TLB miss */
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.org 0xa00
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HANDLE_EXCEPTION
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/* range */
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.org 0xb00
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HANDLE_EXCEPTION
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/* system call */
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.org 0xc00
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HANDLE_EXCEPTION
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/* floating point */
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.org 0xd00
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HANDLE_EXCEPTION
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/* trap */
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.org 0xe00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0xf00
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HANDLE_EXCEPTION
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.org 0x1000
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_crt0:
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/* Setup stack and global pointer */
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l.movhi r1, hi(_fstack)
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l.ori r1, r1, lo(_fstack)
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/* Init DATA */
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l.movhi r14,hi(_fdata_rom)
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l.ori r14,r14,lo(_fdata_rom)
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l.movhi r18,hi(_fdata)
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l.ori r18,r18,lo(_fdata)
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l.movhi r20,hi(_edata)
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l.ori r20,r20,lo(_edata)
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.copyDATA:
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l.sfeq r18,r20
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l.bf .doneDATA
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l.nop
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l.lwz r3,0(r14)
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l.sw 0(r18),r3
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l.addi r14,r14,4
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l.addi r18,r18,4
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l.j .copyDATA
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l.nop
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.doneDATA:
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/* Clear BSS */
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l.movhi r21, hi(_fbss)
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l.ori r21, r21, lo(_fbss)
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l.movhi r3, hi(_ebss)
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l.ori r3, r3, lo(_ebss)
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.clearBSS:
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l.sfeq r21, r3
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l.bf .callMain
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l.nop
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l.sw 0(r21), r0
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l.addi r21, r21, 4
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l.j .clearBSS
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l.nop
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.callMain:
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l.j main
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l.nop
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_exception_handler:
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l.sw 0x00(r1), r2
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l.sw 0x04(r1), r3
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l.sw 0x08(r1), r4
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l.sw 0x0c(r1), r5
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l.sw 0x10(r1), r6
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l.sw 0x14(r1), r7
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l.sw 0x18(r1), r8
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l.sw 0x20(r1), r10
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l.sw 0x24(r1), r11
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l.sw 0x28(r1), r12
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l.sw 0x2c(r1), r13
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l.sw 0x30(r1), r14
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l.sw 0x34(r1), r15
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l.sw 0x38(r1), r16
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l.sw 0x3c(r1), r17
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l.sw 0x40(r1), r18
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l.sw 0x44(r1), r19
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l.sw 0x48(r1), r20
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l.sw 0x4c(r1), r21
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l.sw 0x50(r1), r22
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l.sw 0x54(r1), r23
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l.sw 0x58(r1), r24
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l.sw 0x5c(r1), r25
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l.sw 0x60(r1), r26
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l.sw 0x64(r1), r27
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l.sw 0x68(r1), r28
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l.sw 0x6c(r1), r29
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l.sw 0x70(r1), r30
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l.sw 0x74(r1), r31
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/* Save return address */
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l.or r14, r0, r9
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/* Calculate exception vector from handler address */
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l.andi r3, r9, 0xf00
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l.srli r3, r3, 8
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/* Pass saved register state */
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l.or r4, r0, r1
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/* Extract exception PC */
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l.mfspr r5, r0, SPR_EPCR_BASE
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/* Extract exception effective address */
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l.mfspr r6, r0, SPR_EEAR_BASE
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/* Extract exception SR */
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l.mfspr r7, r0, SPR_ESR_BASE
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/* Call exception handler with the link address as argument */
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l.jal exception_handler
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l.nop
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/* Load return address */
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l.or r9, r0, r14
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/* Restore state */
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l.lwz r2, 0x00(r1)
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l.lwz r3, 0x04(r1)
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l.lwz r4, 0x08(r1)
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l.lwz r5, 0x0c(r1)
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l.lwz r6, 0x10(r1)
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l.lwz r7, 0x14(r1)
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l.lwz r8, 0x18(r1)
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l.lwz r10, 0x20(r1)
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l.lwz r11, 0x24(r1)
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l.lwz r12, 0x28(r1)
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l.lwz r13, 0x2c(r1)
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l.lwz r14, 0x30(r1)
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l.lwz r15, 0x34(r1)
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l.lwz r16, 0x38(r1)
|
||||
l.lwz r17, 0x3c(r1)
|
||||
l.lwz r18, 0x40(r1)
|
||||
l.lwz r19, 0x44(r1)
|
||||
l.lwz r20, 0x48(r1)
|
||||
l.lwz r21, 0x4c(r1)
|
||||
l.lwz r22, 0x50(r1)
|
||||
l.lwz r23, 0x54(r1)
|
||||
l.lwz r24, 0x58(r1)
|
||||
l.lwz r25, 0x5c(r1)
|
||||
l.lwz r26, 0x60(r1)
|
||||
l.lwz r27, 0x64(r1)
|
||||
l.lwz r28, 0x68(r1)
|
||||
l.lwz r29, 0x6c(r1)
|
||||
l.lwz r30, 0x70(r1)
|
||||
l.lwz r31, 0x74(r1)
|
||||
l.jr r9
|
||||
l.nop
|
||||
|
||||
.global _cache_init
|
||||
_cache_init:
|
||||
/*
|
||||
This function is to be used ONLY during reset, before main() is called.
|
||||
TODO: Perhaps break into individual enable instruction/data cache
|
||||
sections functions, and provide disable functions, also, all
|
||||
callable from C
|
||||
*/
|
||||
|
||||
/* Instruction cache enable */
|
||||
/* Check if IC present and skip enabling otherwise */
|
||||
#if 1
|
||||
.L6:
|
||||
l.mfspr r3,r0,SPR_UPR
|
||||
l.andi r7,r3,SPR_UPR_ICP
|
||||
l.sfeq r7,r0
|
||||
l.bf .L8
|
||||
l.nop
|
||||
|
||||
/* Disable IC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.addi r5,r0,-1
|
||||
l.xori r5,r5,SPR_SR_ICE
|
||||
l.and r5,r6,r5
|
||||
l.mtspr r0,r5,SPR_SR
|
||||
|
||||
/* Establish cache block size
|
||||
If BS=0, 16;
|
||||
If BS=1, 32;
|
||||
r14 contain block size
|
||||
*/
|
||||
l.mfspr r3,r0,SPR_ICCFGR
|
||||
l.andi r7,r3,SPR_ICCFGR_CBS
|
||||
l.srli r8,r7,7
|
||||
l.ori r4,r0,16
|
||||
l.sll r14,r4,r8
|
||||
|
||||
/* Establish number of cache sets
|
||||
r10 contains number of cache sets
|
||||
r8 contains log(# of cache sets)
|
||||
*/
|
||||
l.andi r7,r3,SPR_ICCFGR_NCS
|
||||
l.srli r8,r7,3
|
||||
l.ori r4,r0,1
|
||||
l.sll r10,r4,r8
|
||||
|
||||
/* Invalidate IC */
|
||||
l.addi r6,r0,0
|
||||
l.sll r5,r14,r8
|
||||
|
||||
.L7: l.mtspr r0,r6,SPR_ICBIR
|
||||
l.sfne r6,r5
|
||||
l.bf .L7
|
||||
l.add r6,r6,r14
|
||||
|
||||
/* Enable IC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.ori r6,r6,SPR_SR_ICE
|
||||
l.mtspr r0,r6,SPR_SR
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
/* Data cache enable */
|
||||
/* Check if DC present and skip enabling otherwise */
|
||||
#endif
|
||||
.L8:
|
||||
#if 1
|
||||
l.mfspr r3,r0,SPR_UPR
|
||||
l.andi r7,r3,SPR_UPR_DCP
|
||||
l.sfeq r7,r0
|
||||
l.bf .L10
|
||||
l.nop
|
||||
/* Disable DC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.addi r5,r0,-1
|
||||
l.xori r5,r5,SPR_SR_DCE
|
||||
l.and r5,r6,r5
|
||||
l.mtspr r0,r5,SPR_SR
|
||||
/* Establish cache block size
|
||||
If BS=0, 16;
|
||||
If BS=1, 32;
|
||||
r14 contain block size
|
||||
*/
|
||||
l.mfspr r3,r0,SPR_DCCFGR
|
||||
l.andi r7,r3,SPR_DCCFGR_CBS
|
||||
l.srli r8,r7,7
|
||||
l.ori r4,r0,16
|
||||
l.sll r14,r4,r8
|
||||
/* Establish number of cache sets
|
||||
r10 contains number of cache sets
|
||||
r8 contains log(# of cache sets)
|
||||
*/
|
||||
l.andi r7,r3,SPR_DCCFGR_NCS
|
||||
l.srli r8,r7,3
|
||||
l.ori r4,r0,1
|
||||
l.sll r10,r4,r8
|
||||
/* Invalidate DC */
|
||||
l.addi r6,r0,0
|
||||
l.sll r5,r14,r8
|
||||
|
||||
.L9:
|
||||
l.mtspr r0,r6,SPR_DCBIR
|
||||
l.sfne r6,r5
|
||||
l.bf .L9
|
||||
l.add r6,r6,r14
|
||||
/* Enable DC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.ori r6,r6,SPR_SR_DCE
|
||||
l.mtspr r0,r6,SPR_SR
|
||||
#endif
|
||||
.L10:
|
||||
/* Return */
|
||||
l.jr r9
|
||||
l.nop
|
||||
44
litex/soc/cores/cpu/marocchino/irq.h
Normal file
44
litex/soc/cores/cpu/marocchino/irq.h
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#ifndef __IRQ_H
|
||||
#define __IRQ_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <system.h>
|
||||
#include <generated/csr.h>
|
||||
#include <generated/soc.h>
|
||||
|
||||
static inline unsigned int irq_getie(void)
|
||||
{
|
||||
return !!(mfspr(SPR_SR) & SPR_SR_IEE);
|
||||
}
|
||||
|
||||
static inline void irq_setie(unsigned int ie)
|
||||
{
|
||||
if (ie & 0x1)
|
||||
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
|
||||
else
|
||||
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
|
||||
}
|
||||
|
||||
static inline unsigned int irq_getmask(void)
|
||||
{
|
||||
return mfspr(SPR_PICMR);
|
||||
}
|
||||
|
||||
static inline void irq_setmask(unsigned int mask)
|
||||
{
|
||||
mtspr(SPR_PICMR, mask);
|
||||
}
|
||||
|
||||
static inline unsigned int irq_pending(void)
|
||||
{
|
||||
return mfspr(SPR_PICSR);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IRQ_H */
|
||||
696
litex/soc/cores/cpu/marocchino/spr-defs.h
Normal file
696
litex/soc/cores/cpu/marocchino/spr-defs.h
Normal file
|
|
@ -0,0 +1,696 @@
|
|||
/* spr-defs.h - Special purpose registers definitions file
|
||||
|
||||
Copyright (C) 2000 Damjan Lampret
|
||||
Copyright (C) 2008, 2010 Embecosm Limited
|
||||
|
||||
Contributor Damjan Lampret <lampret@opencores.org>
|
||||
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 3 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program. If not, see <http: www.gnu.org/licenses/>. */
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
This code is commented throughout for use with Doxygen.
|
||||
--------------------------------------------------------------------------*/
|
||||
#ifndef SPR_DEFS__H
|
||||
#define SPR_DEFS__H
|
||||
|
||||
/* Definition of special-purpose registers (SPRs). */
|
||||
|
||||
#define MAX_GRPS (32)
|
||||
#define MAX_SPRS_PER_GRP_BITS (11)
|
||||
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
|
||||
#define MAX_SPRS (0x10000)
|
||||
|
||||
/* Base addresses for the groups */
|
||||
#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
|
||||
#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS)
|
||||
|
||||
/* System control and status group */
|
||||
#define SPR_VR (SPRGROUP_SYS + 0)
|
||||
#define SPR_UPR (SPRGROUP_SYS + 1)
|
||||
#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
|
||||
#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
|
||||
#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
|
||||
#define SPR_DCCFGR (SPRGROUP_SYS + 5)
|
||||
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
|
||||
#define SPR_DCFGR (SPRGROUP_SYS + 7)
|
||||
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
|
||||
#define SPR_VR2 (SPRGROUP_SYS + 9)
|
||||
#define SPR_AVR (SPRGROUP_SYS + 10)
|
||||
#define SPR_EVBAR (SPRGROUP_SYS + 11)
|
||||
#define SPR_AECR (SPRGROUP_SYS + 12)
|
||||
#define SPR_AESR (SPRGROUP_SYS + 13)
|
||||
#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
|
||||
#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
|
||||
#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
|
||||
#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */
|
||||
#define SPR_ISR_BASE (SPRGROUP_SYS + 21)
|
||||
#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
|
||||
#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
|
||||
#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
|
||||
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
|
||||
#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
|
||||
#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
|
||||
#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
|
||||
|
||||
/* Data MMU group */
|
||||
#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
|
||||
#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
|
||||
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
|
||||
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
|
||||
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
|
||||
#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
|
||||
|
||||
/* Instruction MMU group */
|
||||
#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
|
||||
#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)
|
||||
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
|
||||
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
|
||||
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
|
||||
#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
|
||||
|
||||
/* Data cache group */
|
||||
#define SPR_DCCR (SPRGROUP_DC + 0)
|
||||
#define SPR_DCBPR (SPRGROUP_DC + 1)
|
||||
#define SPR_DCBFR (SPRGROUP_DC + 2)
|
||||
#define SPR_DCBIR (SPRGROUP_DC + 3)
|
||||
#define SPR_DCBWR (SPRGROUP_DC + 4)
|
||||
#define SPR_DCBLR (SPRGROUP_DC + 5)
|
||||
#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
|
||||
#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
|
||||
|
||||
/* Instruction cache group */
|
||||
#define SPR_ICCR (SPRGROUP_IC + 0)
|
||||
#define SPR_ICBPR (SPRGROUP_IC + 1)
|
||||
#define SPR_ICBIR (SPRGROUP_IC + 2)
|
||||
#define SPR_ICBLR (SPRGROUP_IC + 3)
|
||||
#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
|
||||
#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
|
||||
|
||||
/* MAC group */
|
||||
#define SPR_MACLO (SPRGROUP_MAC + 1)
|
||||
#define SPR_MACHI (SPRGROUP_MAC + 2)
|
||||
|
||||
/* Debug group */
|
||||
#define SPR_DVR(N) (SPRGROUP_D + (N))
|
||||
#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
|
||||
#define SPR_DMR1 (SPRGROUP_D + 16)
|
||||
#define SPR_DMR2 (SPRGROUP_D + 17)
|
||||
#define SPR_DWCR0 (SPRGROUP_D + 18)
|
||||
#define SPR_DWCR1 (SPRGROUP_D + 19)
|
||||
#define SPR_DSR (SPRGROUP_D + 20)
|
||||
#define SPR_DRR (SPRGROUP_D + 21)
|
||||
|
||||
/* Performance counters group */
|
||||
#define SPR_PCCR(N) (SPRGROUP_PC + (N))
|
||||
#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
|
||||
|
||||
/* Power management group */
|
||||
#define SPR_PMR (SPRGROUP_PM + 0)
|
||||
|
||||
/* PIC group */
|
||||
#define SPR_PICMR (SPRGROUP_PIC + 0)
|
||||
#define SPR_PICPR (SPRGROUP_PIC + 1)
|
||||
#define SPR_PICSR (SPRGROUP_PIC + 2)
|
||||
|
||||
/* Tick Timer group */
|
||||
#define SPR_TTMR (SPRGROUP_TT + 0)
|
||||
#define SPR_TTCR (SPRGROUP_TT + 1)
|
||||
|
||||
/*
|
||||
* Bit definitions for the Version Register
|
||||
*
|
||||
*/
|
||||
#define SPR_VR_VER 0xff000000 /* Processor version */
|
||||
#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
|
||||
#define SPR_VR_RES 0x0000ff80 /* Reserved */
|
||||
#define SPR_VR_UVRP 0x00000040 /* Updated version register present */
|
||||
#define SPR_VR_REV 0x0000003f /* Processor revision */
|
||||
|
||||
#define SPR_VR_VER_OFF 24
|
||||
#define SPR_VR_CFG_OFF 16
|
||||
#define SPR_VR_UVRP_OFF 6
|
||||
#define SPR_VR_REV_OFF 0
|
||||
|
||||
/*
|
||||
* Bit definitions for the Unit Present Register
|
||||
*
|
||||
*/
|
||||
#define SPR_UPR_UP 0x00000001 /* UPR present */
|
||||
#define SPR_UPR_DCP 0x00000002 /* Data cache present */
|
||||
#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
|
||||
#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
|
||||
#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
|
||||
#define SPR_UPR_MP 0x00000020 /* MAC present */
|
||||
#define SPR_UPR_DUP 0x00000040 /* Debug unit present */
|
||||
#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */
|
||||
#define SPR_UPR_PMP 0x00000100 /* Power management present */
|
||||
#define SPR_UPR_PICP 0x00000200 /* PIC present */
|
||||
#define SPR_UPR_TTP 0x00000400 /* Tick timer present */
|
||||
#define SPR_UPR_RES 0x00fe0000 /* Reserved */
|
||||
#define SPR_UPR_CUP 0xff000000 /* Context units present */
|
||||
|
||||
/*
|
||||
* JPB: Bit definitions for the CPU configuration register
|
||||
*
|
||||
*/
|
||||
#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
|
||||
#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */
|
||||
#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */
|
||||
#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */
|
||||
#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
|
||||
#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
|
||||
#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
|
||||
#define SPR_CPUCFGR_ND 0x00000400 /* No delay-slot */
|
||||
#define SPR_CPUCFGR_AVRP 0x00000800 /* Architecture version register present */
|
||||
#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception vector base address register
|
||||
present */
|
||||
#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-specific registers present */
|
||||
#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic exception control/status
|
||||
registers present */
|
||||
#define SPR_CPUCFGR_RES 0xffff8000 /* Reserved */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Version Register 2
|
||||
*
|
||||
*/
|
||||
#define SPR_VR2_CPUID 0xff000000 /* Unique CPU identifier */
|
||||
#define SPR_VR2_VER 0x00ffffff /* Version */
|
||||
|
||||
#define SPR_VR2_CPUID_OFF 24
|
||||
#define SPR_VR2_VER_OFF 0
|
||||
|
||||
#define SPR_VR2_CPUID_OR1KSIM 0x00
|
||||
#define SPR_VR2_CPUID_MOR1KX 0x01
|
||||
#define SPR_VR2_CPUID_OR1200 0x12
|
||||
#define SPR_VR2_CPUID_ALTOR32 0x32
|
||||
#define SPR_VR2_CPUID_OR10 0x10
|
||||
|
||||
|
||||
/*
|
||||
* Bit definitions for the Architecture Version register
|
||||
*
|
||||
*/
|
||||
#define SPR_AVR_MAJ 0xff000000 /* Major architecture version number */
|
||||
#define SPR_AVR_MIN 0x00ff0000 /* Minor architecture version number */
|
||||
#define SPR_AVR_REV 0x0000ff00 /* Architecture revision number */
|
||||
#define SPR_AVR_RES 0x000000ff /* Reserved */
|
||||
|
||||
#define SPR_AVR_MAJ_OFF 24
|
||||
#define SPR_AVR_MIN_OFF 16
|
||||
#define SPR_AVR_REV_OFF 8
|
||||
|
||||
/*
|
||||
* Bit definitions for the Exception Base Address register
|
||||
*
|
||||
*/
|
||||
#define SPR_EVBAR_EVBA 0xffffe000 /* Exception vector base address */
|
||||
#define SPR_EVBAR_RES 0x00001fff /* Reserved */
|
||||
|
||||
#define SPR_EVBAR_EVBA_OFF 13
|
||||
|
||||
/*
|
||||
* Bit definitions for the Arithmetic Exception Control register
|
||||
*
|
||||
*/
|
||||
#define SPR_AECR_CYADDE 0x00000001 /* Carry on add/subtract exception */
|
||||
#define SPR_AECR_OVADDE 0x00000002 /* Overflow on add/subtract exception */
|
||||
#define SPR_AECR_CYMULE 0x00000004 /* Carry on multiply exception */
|
||||
#define SPR_AECR_OVMULE 0x00000008 /* Overflow on multiply exception */
|
||||
#define SPR_AECR_DBZE 0x00000010 /* Divide by zero exception */
|
||||
#define SPR_AECR_CYMACADDE 0x00000020 /* Carry on MAC add/subtract exception */
|
||||
#define SPR_AECR_OVMACADDE 0x00000040 /* Overflow on MAC add/subtract exception */
|
||||
|
||||
#define SPR_AECR_CYADDE_OFF 0
|
||||
#define SPR_AECR_OVADDE_OFF 1
|
||||
#define SPR_AECR_CYMULE_OFF 2
|
||||
#define SPR_AECR_OVMULE_OFF 3
|
||||
#define SPR_AECR_DBZE_OFF 4
|
||||
#define SPR_AECR_CYMACADDE_OFF 5
|
||||
#define SPR_AECR_OVMACADDE_OFF 6
|
||||
|
||||
|
||||
/*
|
||||
* Bit definitions for the Arithmetic Exception Status register
|
||||
*
|
||||
*/
|
||||
#define SPR_AESR_CYADDE 0x00000001 /* Carry on add/subtract exception */
|
||||
#define SPR_AESR_OVADDE 0x00000002 /* Overflow on add/subtract exception */
|
||||
#define SPR_AESR_CYMULE 0x00000004 /* Carry on multiply exception */
|
||||
#define SPR_AESR_OVMULE 0x00000008 /* Overflow on multiply exception */
|
||||
#define SPR_AESR_DBZE 0x00000010 /* Divide by zero exception */
|
||||
#define SPR_AESR_CYMACADDE 0x00000020 /* Carry on MAC add/subtract exception */
|
||||
#define SPR_AESR_OVMACADDE 0x00000040 /* Overflow on MAC add/subtract exception */
|
||||
|
||||
#define SPR_AESR_CYADDE_OFF 0
|
||||
#define SPR_AESR_OVADDE_OFF 1
|
||||
#define SPR_AESR_CYMULE_OFF 2
|
||||
#define SPR_AESR_OVMULE_OFF 3
|
||||
#define SPR_AESR_DBZE_OFF 4
|
||||
#define SPR_AESR_CYMACADDE_OFF 5
|
||||
#define SPR_AESR_OVMACADDE_OFF 6
|
||||
|
||||
/*
|
||||
* JPB: Bit definitions for the Debug configuration register and other
|
||||
* constants.
|
||||
*
|
||||
*/
|
||||
|
||||
#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */
|
||||
#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */
|
||||
#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */
|
||||
#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */
|
||||
#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
|
||||
#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
|
||||
#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
|
||||
#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
|
||||
#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
|
||||
#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
|
||||
|
||||
#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
|
||||
2 == n ? SPR_DCFGR_NDP2 : \
|
||||
3 == n ? SPR_DCFGR_NDP3 : \
|
||||
4 == n ? SPR_DCFGR_NDP4 : \
|
||||
5 == n ? SPR_DCFGR_NDP5 : \
|
||||
6 == n ? SPR_DCFGR_NDP6 : \
|
||||
7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
|
||||
#define MAX_MATCHPOINTS 8
|
||||
#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)
|
||||
|
||||
/*
|
||||
* Bit definitions for the Supervision Register
|
||||
*
|
||||
*/
|
||||
#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
|
||||
#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
|
||||
#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
|
||||
#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
|
||||
#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
|
||||
#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
|
||||
#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
|
||||
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
|
||||
#define SPR_SR_CE 0x00000100 /* CID Enable */
|
||||
#define SPR_SR_F 0x00000200 /* Condition Flag */
|
||||
#define SPR_SR_CY 0x00000400 /* Carry flag */
|
||||
#define SPR_SR_OV 0x00000800 /* Overflow flag */
|
||||
#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
|
||||
#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
|
||||
#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
|
||||
#define SPR_SR_FO 0x00008000 /* Fixed one */
|
||||
#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
|
||||
#define SPR_SR_RES 0x0ffe0000 /* Reserved */
|
||||
#define SPR_SR_CID 0xf0000000 /* Context ID */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Data MMU Control Register
|
||||
*
|
||||
*/
|
||||
#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
|
||||
#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
|
||||
#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
|
||||
#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Instruction MMU Control Register
|
||||
*
|
||||
*/
|
||||
#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
|
||||
#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
|
||||
#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
|
||||
#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Data TLB Match Register
|
||||
*
|
||||
*/
|
||||
#define SPR_DTLBMR_V 0x00000001 /* Valid */
|
||||
#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
|
||||
#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
|
||||
#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
|
||||
#define SPR_DTLBMR_VPN 0xffffe000 /* Virtual Page Number */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Data TLB Translate Register
|
||||
*
|
||||
*/
|
||||
#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
|
||||
#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
|
||||
#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
|
||||
#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
|
||||
#define SPR_DTLBTR_A 0x00000010 /* Accessed */
|
||||
#define SPR_DTLBTR_D 0x00000020 /* Dirty */
|
||||
#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
|
||||
#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
|
||||
#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
|
||||
#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
|
||||
#define SPR_DTLBTR_PPN 0xffffe000 /* Physical Page Number */
|
||||
|
||||
#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_URE | \
|
||||
SPR_DTLBTR_UWE | \
|
||||
SPR_DTLBTR_SRE | \
|
||||
SPR_DTLBTR_SWE )
|
||||
|
||||
/*
|
||||
* Bit definitions for the Instruction TLB Match Register
|
||||
*
|
||||
*/
|
||||
#define SPR_ITLBMR_V 0x00000001 /* Valid */
|
||||
#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
|
||||
#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
|
||||
#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
|
||||
#define SPR_ITLBMR_VPN 0xffffe000 /* Virtual Page Number */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Instruction TLB Translate Register
|
||||
*
|
||||
*/
|
||||
#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
|
||||
#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
|
||||
#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
|
||||
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
|
||||
#define SPR_ITLBTR_A 0x00000010 /* Accessed */
|
||||
#define SPR_ITLBTR_D 0x00000020 /* Dirty */
|
||||
#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
|
||||
#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
|
||||
#define SPR_ITLBTR_PPN 0xffffe000 /* Physical Page Number */
|
||||
|
||||
#define ITLB_PR_NOLIMIT ( SPR_ITLBTR_SXE | \
|
||||
SPR_ITLBTR_UXE )
|
||||
|
||||
|
||||
/*
|
||||
* Bit definitions for Data Cache Control register
|
||||
*
|
||||
*/
|
||||
#define SPR_DCCR_EW 0x000000ff /* Enable ways */
|
||||
|
||||
/*
|
||||
* Bit definitions for Insn Cache Control register
|
||||
*
|
||||
*/
|
||||
#define SPR_ICCR_EW 0x000000ff /* Enable ways */
|
||||
|
||||
/*
|
||||
* Bit definitions for Data Cache Configuration Register
|
||||
*
|
||||
*/
|
||||
|
||||
#define SPR_DCCFGR_NCW 0x00000007
|
||||
#define SPR_DCCFGR_NCS 0x00000078
|
||||
#define SPR_DCCFGR_CBS 0x00000080
|
||||
#define SPR_DCCFGR_CWS 0x00000100
|
||||
#define SPR_DCCFGR_CCRI 0x00000200
|
||||
#define SPR_DCCFGR_CBIRI 0x00000400
|
||||
#define SPR_DCCFGR_CBPRI 0x00000800
|
||||
#define SPR_DCCFGR_CBLRI 0x00001000
|
||||
#define SPR_DCCFGR_CBFRI 0x00002000
|
||||
#define SPR_DCCFGR_CBWBRI 0x00004000
|
||||
|
||||
#define SPR_DCCFGR_NCW_OFF 0
|
||||
#define SPR_DCCFGR_NCS_OFF 3
|
||||
#define SPR_DCCFGR_CBS_OFF 7
|
||||
|
||||
/*
|
||||
* Bit definitions for Instruction Cache Configuration Register
|
||||
*
|
||||
*/
|
||||
#define SPR_ICCFGR_NCW 0x00000007
|
||||
#define SPR_ICCFGR_NCS 0x00000078
|
||||
#define SPR_ICCFGR_CBS 0x00000080
|
||||
#define SPR_ICCFGR_CCRI 0x00000200
|
||||
#define SPR_ICCFGR_CBIRI 0x00000400
|
||||
#define SPR_ICCFGR_CBPRI 0x00000800
|
||||
#define SPR_ICCFGR_CBLRI 0x00001000
|
||||
|
||||
#define SPR_ICCFGR_NCW_OFF 0
|
||||
#define SPR_ICCFGR_NCS_OFF 3
|
||||
#define SPR_ICCFGR_CBS_OFF 7
|
||||
|
||||
/*
|
||||
* Bit definitions for Data MMU Configuration Register
|
||||
*
|
||||
*/
|
||||
|
||||
#define SPR_DMMUCFGR_NTW 0x00000003
|
||||
#define SPR_DMMUCFGR_NTS 0x0000001C
|
||||
#define SPR_DMMUCFGR_NAE 0x000000E0
|
||||
#define SPR_DMMUCFGR_CRI 0x00000100
|
||||
#define SPR_DMMUCFGR_PRI 0x00000200
|
||||
#define SPR_DMMUCFGR_TEIRI 0x00000400
|
||||
#define SPR_DMMUCFGR_HTR 0x00000800
|
||||
|
||||
#define SPR_DMMUCFGR_NTW_OFF 0
|
||||
#define SPR_DMMUCFGR_NTS_OFF 2
|
||||
|
||||
/*
|
||||
* Bit definitions for Instruction MMU Configuration Register
|
||||
*
|
||||
*/
|
||||
|
||||
#define SPR_IMMUCFGR_NTW 0x00000003
|
||||
#define SPR_IMMUCFGR_NTS 0x0000001C
|
||||
#define SPR_IMMUCFGR_NAE 0x000000E0
|
||||
#define SPR_IMMUCFGR_CRI 0x00000100
|
||||
#define SPR_IMMUCFGR_PRI 0x00000200
|
||||
#define SPR_IMMUCFGR_TEIRI 0x00000400
|
||||
#define SPR_IMMUCFGR_HTR 0x00000800
|
||||
|
||||
#define SPR_IMMUCFGR_NTW_OFF 0
|
||||
#define SPR_IMMUCFGR_NTS_OFF 2
|
||||
|
||||
/*
|
||||
* Bit definitions for Debug Control registers
|
||||
*
|
||||
*/
|
||||
#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
|
||||
#define SPR_DCR_CC 0x0000000e /* Compare condition */
|
||||
#define SPR_DCR_SC 0x00000010 /* Signed compare */
|
||||
#define SPR_DCR_CT 0x000000e0 /* Compare to */
|
||||
|
||||
/* Bit results with SPR_DCR_CC mask */
|
||||
#define SPR_DCR_CC_MASKED 0x00000000
|
||||
#define SPR_DCR_CC_EQUAL 0x00000002
|
||||
#define SPR_DCR_CC_LESS 0x00000004
|
||||
#define SPR_DCR_CC_LESSE 0x00000006
|
||||
#define SPR_DCR_CC_GREAT 0x00000008
|
||||
#define SPR_DCR_CC_GREATE 0x0000000a
|
||||
#define SPR_DCR_CC_NEQUAL 0x0000000c
|
||||
|
||||
/* Bit results with SPR_DCR_CT mask */
|
||||
#define SPR_DCR_CT_DISABLED 0x00000000
|
||||
#define SPR_DCR_CT_IFEA 0x00000020
|
||||
#define SPR_DCR_CT_LEA 0x00000040
|
||||
#define SPR_DCR_CT_SEA 0x00000060
|
||||
#define SPR_DCR_CT_LD 0x00000080
|
||||
#define SPR_DCR_CT_SD 0x000000a0
|
||||
#define SPR_DCR_CT_LSEA 0x000000c0
|
||||
#define SPR_DCR_CT_LSD 0x000000e0
|
||||
/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
|
||||
|
||||
/*
|
||||
* Bit definitions for Debug Mode 1 register
|
||||
*
|
||||
*/
|
||||
#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */
|
||||
#define SPR_DMR1_CW0_AND 0x00000001
|
||||
#define SPR_DMR1_CW0_OR 0x00000002
|
||||
#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
|
||||
#define SPR_DMR1_CW1_AND 0x00000004
|
||||
#define SPR_DMR1_CW1_OR 0x00000008
|
||||
#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
|
||||
#define SPR_DMR1_CW2_AND 0x00000010
|
||||
#define SPR_DMR1_CW2_OR 0x00000020
|
||||
#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
|
||||
#define SPR_DMR1_CW3_AND 0x00000040
|
||||
#define SPR_DMR1_CW3_OR 0x00000080
|
||||
#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
|
||||
#define SPR_DMR1_CW4_AND 0x00000100
|
||||
#define SPR_DMR1_CW4_OR 0x00000200
|
||||
#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
|
||||
#define SPR_DMR1_CW5_AND 0x00000400
|
||||
#define SPR_DMR1_CW5_OR 0x00000800
|
||||
#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
|
||||
#define SPR_DMR1_CW6_AND 0x00001000
|
||||
#define SPR_DMR1_CW6_OR 0x00002000
|
||||
#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
|
||||
#define SPR_DMR1_CW7_AND 0x00004000
|
||||
#define SPR_DMR1_CW7_OR 0x00008000
|
||||
#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
|
||||
#define SPR_DMR1_CW8_AND 0x00010000
|
||||
#define SPR_DMR1_CW8_OR 0x00020000
|
||||
#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
|
||||
#define SPR_DMR1_CW9_AND 0x00040000
|
||||
#define SPR_DMR1_CW9_OR 0x00080000
|
||||
#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
|
||||
#define SPR_DMR1_RES1 0x00300000 /* Reserved */
|
||||
#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
|
||||
#define SPR_DMR1_BT 0x00800000 /* Branch trace */
|
||||
#define SPR_DMR1_RES2 0xff000000 /* Reserved */
|
||||
|
||||
/*
|
||||
* Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
|
||||
*
|
||||
*/
|
||||
#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
|
||||
#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
|
||||
#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */
|
||||
#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */
|
||||
#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
|
||||
#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */
|
||||
#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */
|
||||
#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */
|
||||
|
||||
/*
|
||||
* Bit definitions for Debug watchpoint counter registers
|
||||
*
|
||||
*/
|
||||
#define SPR_DWCR_COUNT 0x0000ffff /* Count */
|
||||
#define SPR_DWCR_MATCH 0xffff0000 /* Match */
|
||||
#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */
|
||||
|
||||
/*
|
||||
* Bit definitions for Debug stop register
|
||||
*
|
||||
*/
|
||||
#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
|
||||
#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
|
||||
#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
|
||||
#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
|
||||
#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */
|
||||
#define SPR_DSR_AE 0x00000020 /* Alignment exception */
|
||||
#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
|
||||
#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
|
||||
#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
|
||||
#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
|
||||
#define SPR_DSR_RE 0x00000400 /* Range exception */
|
||||
#define SPR_DSR_SCE 0x00000800 /* System call exception */
|
||||
#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
|
||||
#define SPR_DSR_TE 0x00002000 /* Trap exception */
|
||||
|
||||
/*
|
||||
* Bit definitions for Debug reason register
|
||||
*
|
||||
*/
|
||||
#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
|
||||
#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
|
||||
#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
|
||||
#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
|
||||
#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
|
||||
#define SPR_DRR_AE 0x00000020 /* Alignment exception */
|
||||
#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
|
||||
#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
|
||||
#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
|
||||
#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
|
||||
#define SPR_DRR_RE 0x00000400 /* Range exception */
|
||||
#define SPR_DRR_SCE 0x00000800 /* System call exception */
|
||||
#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
|
||||
#define SPR_DRR_TE 0x00002000 /* Trap exception */
|
||||
|
||||
/*
|
||||
* Bit definitions for Performance counters mode registers
|
||||
*
|
||||
*/
|
||||
#define SPR_PCMR_CP 0x00000001 /* Counter present */
|
||||
#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
|
||||
#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
|
||||
#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
|
||||
#define SPR_PCMR_LA 0x00000010 /* Load access event */
|
||||
#define SPR_PCMR_SA 0x00000020 /* Store access event */
|
||||
#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
|
||||
#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
|
||||
#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
|
||||
#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
|
||||
#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
|
||||
#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
|
||||
#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
|
||||
#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
|
||||
#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
|
||||
#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Power management register
|
||||
*
|
||||
*/
|
||||
#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
|
||||
#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
|
||||
#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
|
||||
#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
|
||||
#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
|
||||
|
||||
/*
|
||||
* Bit definitions for PICMR
|
||||
*
|
||||
*/
|
||||
#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
|
||||
|
||||
/*
|
||||
* Bit definitions for PICPR
|
||||
*
|
||||
*/
|
||||
#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
|
||||
|
||||
/*
|
||||
* Bit definitions for PICSR
|
||||
*
|
||||
*/
|
||||
#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
|
||||
|
||||
/*
|
||||
* Bit definitions for Tick Timer Control Register
|
||||
*
|
||||
*/
|
||||
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
|
||||
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
|
||||
#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
|
||||
#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
|
||||
#define SPR_TTMR_RT 0x40000000 /* Restart tick */
|
||||
#define SPR_TTMR_SR 0x80000000 /* Single run */
|
||||
#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
|
||||
#define SPR_TTMR_M 0xc0000000 /* Tick mode */
|
||||
|
||||
/*
|
||||
* Bit definitions for the FP Control Status Register
|
||||
*
|
||||
*/
|
||||
#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
|
||||
#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
|
||||
#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
|
||||
#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
|
||||
#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
|
||||
#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
|
||||
#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
|
||||
#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
|
||||
#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
|
||||
#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
|
||||
#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
|
||||
#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
|
||||
SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
|
||||
SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
|
||||
|
||||
#define FPCSR_RM_RN (0<<1)
|
||||
#define FPCSR_RM_RZ (1<<1)
|
||||
#define FPCSR_RM_RIP (2<<1)
|
||||
#define FPCSR_RM_RIN (3<<1)
|
||||
|
||||
#endif /* SPR_DEFS__H */
|
||||
71
litex/soc/cores/cpu/marocchino/system.h
Normal file
71
litex/soc/cores/cpu/marocchino/system.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
#ifndef __SYSTEM_H
|
||||
#define __SYSTEM_H
|
||||
|
||||
#include <spr-defs.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline unsigned long mfspr(unsigned long add)
|
||||
{
|
||||
unsigned long ret;
|
||||
|
||||
__asm__ __volatile__ ("l.mfspr %0,%1,0" : "=r" (ret) : "r" (add));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void mtspr(unsigned long add, unsigned long val)
|
||||
{
|
||||
__asm__ __volatile__ ("l.mtspr %0,%1,0" : : "r" (add), "r" (val));
|
||||
}
|
||||
|
||||
__attribute__((unused)) static void flush_cpu_icache(void)
|
||||
{
|
||||
unsigned long iccfgr;
|
||||
unsigned long cache_set_size;
|
||||
unsigned long cache_ways;
|
||||
unsigned long cache_block_size;
|
||||
unsigned long cache_size;
|
||||
int i;
|
||||
|
||||
iccfgr = mfspr(SPR_ICCFGR);
|
||||
cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
|
||||
cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
|
||||
cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
|
||||
cache_size = cache_set_size * cache_ways * cache_block_size;
|
||||
|
||||
for (i = 0; i < cache_size; i += cache_block_size)
|
||||
mtspr(SPR_ICBIR, i);
|
||||
}
|
||||
|
||||
__attribute__((unused)) static void flush_cpu_dcache(void)
|
||||
{
|
||||
unsigned long dccfgr;
|
||||
unsigned long cache_set_size;
|
||||
unsigned long cache_ways;
|
||||
unsigned long cache_block_size;
|
||||
unsigned long cache_size;
|
||||
int i;
|
||||
|
||||
dccfgr = mfspr(SPR_DCCFGR);
|
||||
cache_ways = 1 << (dccfgr & SPR_ICCFGR_NCW);
|
||||
cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
|
||||
cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
|
||||
cache_size = cache_set_size * cache_ways * cache_block_size;
|
||||
|
||||
for (i = 0; i < cache_size; i += cache_block_size)
|
||||
mtspr(SPR_DCBIR, i);
|
||||
}
|
||||
|
||||
void flush_l2_cache(void);
|
||||
|
||||
void busy_wait(unsigned int ms);
|
||||
void busy_wait_us(unsigned int us);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_H */
|
||||
Loading…
Reference in a new issue