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inteconnect/stream: cleanup
This commit is contained in:
Florent Kermarrec
parent
cafd9c358a
commit
1c88c0f896
1 changed files with 65 additions and 67 deletions
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@ -31,10 +31,10 @@ def _make_m2s(layout):
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class EndpointDescription:
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def __init__(self, payload_layout, param_layout=[]):
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self.payload_layout = payload_layout
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self.param_layout = param_layout
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self.param_layout = param_layout
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def get_full_layout(self):
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reserved = {"valid", "ready", "payload", "param", "first", "last", "description"}
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reserved = {"valid", "ready", "payload", "param", "first", "last", "description"}
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attributed = set()
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for f in self.payload_layout + self.param_layout:
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if f[0] in attributed:
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@ -44,12 +44,12 @@ class EndpointDescription:
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attributed.add(f[0])
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full_layout = [
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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("first", 1, DIR_M_TO_S),
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("last", 1, DIR_M_TO_S),
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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("first", 1, DIR_M_TO_S),
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("last", 1, DIR_M_TO_S),
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("payload", _make_m2s(self.payload_layout)),
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("param", _make_m2s(self.param_layout))
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("param", _make_m2s(self.param_layout))
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]
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return full_layout
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@ -117,11 +117,11 @@ class PipelinedActor(BinaryActor):
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def __init__(self, latency):
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self.latency = latency
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self.pipe_ce = Signal()
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self.busy = Signal()
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self.busy = Signal()
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BinaryActor.__init__(self, latency)
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def build_binary_control(self, sink, source, latency):
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busy = 0
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busy = 0
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valid = sink.valid
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for i in range(latency):
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valid_n = Signal()
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@ -136,7 +136,7 @@ class PipelinedActor(BinaryActor):
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self.busy.eq(busy)
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]
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first = sink.valid & sink.first
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last = sink.valid & sink.last
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last = sink.valid & sink.last
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for i in range(latency):
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first_n = Signal()
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last_n = Signal()
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@ -156,19 +156,21 @@ class PipelinedActor(BinaryActor):
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class _FIFOWrapper(Module):
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def __init__(self, fifo_class, layout, depth):
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self.sink = Endpoint(layout)
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self.sink = Endpoint(layout)
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self.source = Endpoint(layout)
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# # #
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description = self.sink.description
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fifo_layout = [("payload", description.payload_layout),
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("param", description.param_layout),
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("first", 1),
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("last", 1)]
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fifo_layout = [
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("payload", description.payload_layout),
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("param", description.param_layout),
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("first", 1),
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("last", 1)
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]
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self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth)
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fifo_in = Record(fifo_layout)
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fifo_in = Record(fifo_layout)
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fifo_out = Record(fifo_layout)
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self.comb += [
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self.fifo.din.eq(fifo_in.raw_bits()),
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@ -194,20 +196,20 @@ class _FIFOWrapper(Module):
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class SyncFIFO(_FIFOWrapper):
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def __init__(self, layout, depth, buffered=False):
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_FIFOWrapper.__init__(
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self,
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fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
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layout, depth)
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_FIFOWrapper.__init__(self,
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fifo_class = fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
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layout = layout,
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depth = depth)
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self.depth = self.fifo.depth
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self.level = self.fifo.level
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class AsyncFIFO(_FIFOWrapper):
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def __init__(self, layout, depth, buffered=False):
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_FIFOWrapper.__init__(
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self,
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fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
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layout, depth)
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_FIFOWrapper.__init__(self,
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fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
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layout = layout,
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depth = depth)
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# Mux/Demux ----------------------------------------------------------------------------------------
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@ -250,16 +252,15 @@ class Demultiplexer(Module):
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class _UpConverter(Module):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to),
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("valid_token_count", bits_for(ratio))])
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to), ("valid_token_count", bits_for(ratio))])
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self.latency = 1
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# # #
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# control path
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demux = Signal(max=ratio)
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load_part = Signal()
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# Control path
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demux = Signal(max=ratio)
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load_part = Signal()
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strobe_all = Signal()
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self.comb += [
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sink.ready.eq(~strobe_all | source.ready),
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@ -293,30 +294,29 @@ class _UpConverter(Module):
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)
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]
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# data path
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# Data path
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cases = {}
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for i in range(ratio):
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n = ratio-i-1 if reverse else i
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cases[i] = source.data[n*nbits_from:(n+1)*nbits_from].eq(sink.data)
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self.sync += If(load_part, Case(demux, cases))
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# valid token count
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# Valid token count
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self.sync += If(load_part, source.valid_token_count.eq(demux + 1))
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class _DownConverter(Module):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to),
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("valid_token_count", 1)])
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to), ("valid_token_count", 1)])
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self.latency = 0
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# # #
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# control path
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mux = Signal(max=ratio)
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# Control path
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mux = Signal(max=ratio)
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first = Signal()
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last = Signal()
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last = Signal()
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self.comb += [
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first.eq(mux == 0),
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last.eq(mux == (ratio-1)),
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@ -334,22 +334,21 @@ class _DownConverter(Module):
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)
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)
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# data path
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# Data path
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cases = {}
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for i in range(ratio):
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n = ratio-i-1 if reverse else i
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cases[i] = source.data.eq(sink.data[n*nbits_to:(n+1)*nbits_to])
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self.comb += Case(mux, cases).makedefault()
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# valid token count
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# Valid token count
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self.comb += source.valid_token_count.eq(last)
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class _IdentityConverter(Module):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to),
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("valid_token_count", 1)])
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to), ("valid_token_count", 1)])
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self.latency = 0
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# # #
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@ -374,13 +373,13 @@ def _get_converter_ratio(nbits_from, nbits_to):
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else:
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converter_cls = _IdentityConverter
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ratio = 1
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return converter_cls, ratio
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class Converter(Module):
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def __init__(self, nbits_from, nbits_to, reverse=False,
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report_valid_token_count=False):
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def __init__(self, nbits_from, nbits_to,
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reverse = False,
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report_valid_token_count = False):
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self.cls, self.ratio = _get_converter_ratio(nbits_from, nbits_to)
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# # #
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@ -394,24 +393,23 @@ class Converter(Module):
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self.source = converter.source
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else:
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self.source = Endpoint([("data", nbits_to)])
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self.comb += converter.source.connect(self.source,
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omit=set(["valid_token_count"]))
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self.comb += converter.source.connect(self.source, omit=set(["valid_token_count"]))
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class StrideConverter(Module):
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def __init__(self, description_from, description_to, reverse=False):
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self.sink = sink = Endpoint(description_from)
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self.sink = sink = Endpoint(description_from)
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self.source = source = Endpoint(description_to)
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# # #
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nbits_from = len(sink.payload.raw_bits())
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nbits_to = len(source.payload.raw_bits())
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nbits_to = len(source.payload.raw_bits())
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converter = Converter(nbits_from, nbits_to, reverse)
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self.submodules += converter
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# cast sink to converter.sink (user fields --> raw bits)
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# Cast sink to converter.sink (user fields --> raw bits)
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self.comb += [
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converter.sink.valid.eq(sink.valid),
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converter.sink.first.eq(sink.first),
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@ -431,7 +429,7 @@ class StrideConverter(Module):
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self.comb += converter.sink.data.eq(sink.payload.raw_bits())
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# cast converter.source to source (raw bits --> user fields)
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# Cast converter.source to source (raw bits --> user fields)
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self.comb += [
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source.valid.eq(converter.source.valid),
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source.first.eq(converter.source.first),
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@ -450,7 +448,7 @@ class StrideConverter(Module):
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else:
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self.comb += source.payload.raw_bits().eq(converter.source.data)
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# connect params
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# Connect params
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if converter.latency == 0:
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self.comb += source.param.eq(sink.param)
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elif converter.latency == 1:
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@ -477,11 +475,11 @@ class Gearbox(Module):
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io_lcm = lcm(i_dw, o_dw)
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# control path
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# Control path
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level = Signal(max=io_lcm)
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i_inc = Signal()
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i_count = Signal(max=io_lcm//i_dw)
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level = Signal(max=io_lcm)
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i_inc = Signal()
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i_count = Signal(max=io_lcm//i_dw)
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o_inc = Signal()
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o_count = Signal(max=io_lcm//o_dw)
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@ -498,10 +496,10 @@ class Gearbox(Module):
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If(o_inc, *inc_mod(o_count, io_lcm//o_dw)),
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If(i_inc & ~o_inc, level.eq(level + i_dw)),
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If(~i_inc & o_inc, level.eq(level - o_dw)),
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If(i_inc & o_inc, level.eq(level + i_dw - o_dw))
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If(i_inc & o_inc, level.eq(level + i_dw - o_dw)),
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]
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# data path
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# Data path
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shift_register = Signal(io_lcm)
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@ -529,9 +527,9 @@ class Gearbox(Module):
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class Monitor(Module, AutoCSR):
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def __init__(self, endpoint, count_width=32, clock_domain="sys",
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with_tokens=False,
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with_overflows=False,
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with_underflows=False):
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with_tokens = False,
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with_overflows = False,
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with_underflows = False):
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self.reset = CSR()
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self.latch = CSR()
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@ -561,7 +559,7 @@ class Monitor(Module, AutoCSR):
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# Generic Monitor Counter ------------------------------------------------------------------
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class MonitorCounter(Module):
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def __init__(self, reset, latch, enable, count):
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_count = Signal.like(count)
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_count = Signal.like(count)
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_count_latched = Signal.like(count)
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_sync = getattr(self.sync, clock_domain)
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_sync += [
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@ -598,7 +596,7 @@ class Monitor(Module, AutoCSR):
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class Buffer(PipelinedActor):
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def __init__(self, layout):
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self.sink = Endpoint(layout)
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self.sink = Endpoint(layout)
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self.source = Endpoint(layout)
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PipelinedActor.__init__(self, 1)
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self.sync += \
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@ -664,7 +662,7 @@ class PipeReady(Module):
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class Cast(CombinatorialActor):
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def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False):
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self.sink = Endpoint(_rawbits_layout(layout_from))
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self.sink = Endpoint(_rawbits_layout(layout_from))
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self.source = Endpoint(_rawbits_layout(layout_to))
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CombinatorialActor.__init__(self)
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@ -691,9 +689,9 @@ class Unpack(Module):
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# # #
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mux = Signal(max=n)
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mux = Signal(max=n)
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first = Signal()
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last = Signal()
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last = Signal()
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self.comb += [
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first.eq(mux == 0),
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last.eq(mux == (n-1)),
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