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Merge pull request #1390 from tpwrules/add-linux-vexriscv_smp 

cores/cpu/vexriscv_smp: add default cores used by linux with l2 cache
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Dolu1990 2022-08-04 12:19:37 +02:00 committed by GitHub
parent 6932fc51e2 35e0de043d
commit 1ce378e24d
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 10 additions and 4 deletions
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12
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -176,7 +176,11 @@ class VexRiscvSMP(CPU):
@staticmethod
def generate_default_configs():
# Single cores.
for data_width in [16, 32, 64, 128]:
for data_width in [None, 16, 32, 64, 128]:
if data_width is None:
VexRiscvSMP.wishbone_memory = True
else:
VexRiscvSMP.wishbone_memory = False
VexRiscvSMP.litedram_width = data_width
VexRiscvSMP.icache_width = 32
VexRiscvSMP.dcache_width = 32
@ -204,8 +208,10 @@ class VexRiscvSMP(CPU):
VexRiscvSMP.icache_size = 8192
VexRiscvSMP.dcache_ways = 2
VexRiscvSMP.icache_ways = 2
VexRiscvSMP.icache_width = 32 if data_width < 64 else 64
VexRiscvSMP.dcache_width = 32 if data_width < 64 else 64
VexRiscvSMP.icache_width = 32 if data_width is None \
or data_width < 64 else 64
VexRiscvSMP.dcache_width = 32 if data_width is None \
or data_width < 64 else 64
# Without DMA.
VexRiscvSMP.coherent_dma = False