modify TestDesign to be able to simulate phy with host <--> device loopback
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@ -67,7 +67,16 @@ _io = [
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IOStandard("LVCMOS25")
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IOStandard("LVCMOS25")
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),
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),
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("sata", 0,
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("sata_host", 0,
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Subsignal("refclk_p", Pins("YYY")),
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Subsignal("refclk_n", Pins("YYY")),
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Subsignal("txp", Pins("YYY")),
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Subsignal("txn", Pins("YYY")),
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Subsignal("rxp", Pins("YYY")),
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Subsignal("rxn", Pins("YYY")),
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),
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("sata_device", 0,
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Subsignal("refclk_p", Pins("YYY")),
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Subsignal("refclk_p", Pins("YYY")),
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Subsignal("refclk_n", Pins("YYY")),
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Subsignal("refclk_n", Pins("YYY")),
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Subsignal("txp", Pins("YYY")),
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Subsignal("txp", Pins("YYY")),
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@ -94,6 +94,7 @@ class TestDesign(UART2WB):
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UART2WB.__init__(self, platform, clk_freq)
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UART2WB.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform)
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self.submodules.sataphy = K7SATAPHY(platform.request("sata"))
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self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), host=True)
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self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), host=False)
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default_subtarget = TestDesign
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default_subtarget = TestDesign
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