modify TestDesign to be able to simulate phy with host <--> device loopback
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parent
7e14c4fc51
commit
1d053bd7ee
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@ -34,31 +34,31 @@ _io = [
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
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("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
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("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
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("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
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("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
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("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
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("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
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("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
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("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
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("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
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("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
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("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
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("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
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("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
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("clk200", 0,
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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),
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("clk156", 0,
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("clk156", 0,
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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),
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),
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("serial", 0,
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("serial", 0,
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Subsignal("cts", Pins("L27")),
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Subsignal("cts", Pins("L27")),
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Subsignal("rts", Pins("K23")),
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Subsignal("rts", Pins("K23")),
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@ -66,8 +66,17 @@ _io = [
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Subsignal("rx", Pins("M19")),
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Subsignal("rx", Pins("M19")),
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IOStandard("LVCMOS25")
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IOStandard("LVCMOS25")
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),
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),
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("sata", 0,
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("sata_host", 0,
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Subsignal("refclk_p", Pins("YYY")),
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Subsignal("refclk_n", Pins("YYY")),
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Subsignal("txp", Pins("YYY")),
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Subsignal("txn", Pins("YYY")),
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Subsignal("rxp", Pins("YYY")),
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Subsignal("rxn", Pins("YYY")),
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),
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("sata_device", 0,
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Subsignal("refclk_p", Pins("YYY")),
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Subsignal("refclk_p", Pins("YYY")),
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Subsignal("refclk_n", Pins("YYY")),
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Subsignal("refclk_n", Pins("YYY")),
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Subsignal("txp", Pins("YYY")),
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Subsignal("txp", Pins("YYY")),
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@ -102,5 +111,5 @@ def Platform(*args, toolchain="vivado", **kwargs):
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try:
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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except ConstraintError:
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except ConstraintError:
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pass
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pass
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return RealPlatform(*args, **kwargs)
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return RealPlatform(*args, **kwargs)
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@ -94,6 +94,7 @@ class TestDesign(UART2WB):
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UART2WB.__init__(self, platform, clk_freq)
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UART2WB.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform)
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self.submodules.sataphy = K7SATAPHY(platform.request("sata"))
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self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), host=True)
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self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), host=False)
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default_subtarget = TestDesign
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default_subtarget = TestDesign
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