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modify TestDesign to be able to simulate phy with host <--> device loopback

This commit is contained in:
Florent Kermarrec 2014-09-25 15:37:49 +02:00
parent 7e14c4fc51
commit 1d053bd7ee
2 changed files with 21 additions and 11 deletions
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11
platforms/kc705_impact.py
View File

@ -67,7 +67,16 @@ _io = [
IOStandard("LVCMOS25")
),
("sata", 0,
("sata_host", 0,
Subsignal("refclk_p", Pins("YYY")),
Subsignal("refclk_n", Pins("YYY")),
Subsignal("txp", Pins("YYY")),
Subsignal("txn", Pins("YYY")),
Subsignal("rxp", Pins("YYY")),
Subsignal("rxn", Pins("YYY")),
),
("sata_device", 0,
Subsignal("refclk_p", Pins("YYY")),
Subsignal("refclk_n", Pins("YYY")),
Subsignal("txp", Pins("YYY")),

3
targets/test.py
View File

@ -94,6 +94,7 @@ class TestDesign(UART2WB):
UART2WB.__init__(self, platform, clk_freq)
self.submodules.crg = _CRG(platform)
self.submodules.sataphy = K7SATAPHY(platform.request("sata"))
self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), host=True)
self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), host=False)
default_subtarget = TestDesign