ip: add skeleton
This commit is contained in:
Florent Kermarrec
parent
41ead49c76
commit
1d447f2ae1
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@ -2,25 +2,23 @@ from liteeth.common import *
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from liteeth.generic.arbiter import Arbiter
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from liteeth.generic.dispatcher import Dispatcher
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from liteeth.mac import LiteEthMAC
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from liteeth.arp import LiteEthARP
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from liteeth.ip import LiteEthIP
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class LiteEthIPStack(Module, AutoCSR):
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def __init__(self, phy,
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mac_address= 0x12345678abcd,
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ip_address="192.168.0.10"):
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def __init__(self, phy, mac_address, ip_address):
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self.phy = phy
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self.submodules.mac = mac = LiteEthMAC(phy, 8, interface="mac", with_hw_preamble_crc=True)
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self.submodules.arp = arp = LiteEthARP(mac_address, ip_address)
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self.submodules.ip = ip = LiteEthMACIP()
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self.submodules.ip = ip = LiteEthIP(ip_address, arp.table)
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# MAC dispatch
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self.submodules.mac_dispatcher = mac_dispatcher = Dispatcher(mac.source, [arp.sink, ip.sink], one_hot=True)
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self.submodules.mac_dispatcher = Dispatcher(mac.source, [arp.sink, ip.sink], one_hot=True)
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self.comb += \
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Case(mac.source.eth_type, {
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ethernet_type_arp : [mac_dispatcher.sel.eq(1)],
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ethernet_type_ip : [mac_dispatcher.sel.eq(2)],
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"default" : [mac_dispatcher.sel.eq(0)],
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Case(mac.source.ethernet_type, {
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ethernet_type_arp : [self.mac_dispatcher.sel.eq(1)],
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ethernet_type_ip : [self.mac_dispatcher.sel.eq(2)],
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"default" : [self.mac_dispatcher.sel.eq(0)],
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})
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# MAC arbitrate
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self.submodules.mac_arbiter = mac_arbiter = Arbiter([arp.source, ip.source], mac.sink)
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self.submodules.mac_arbiter = Arbiter([arp.source, ip.source], mac.sink)
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@ -96,6 +96,7 @@ class LiteEthARPRX(Module):
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("CHECK")
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)
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)
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@ -134,15 +135,6 @@ class LiteEthARPRX(Module):
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)
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)
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arp_table_request_layout = [
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("ip_address", 32)
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]
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arp_table_response_layout = [
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("failed", 1),
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("mac_address", 48)
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]
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class LiteEthARPTable(Module):
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def __init__(self):
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self.sink = sink = Sink(_arp_table_layout) # from arp_rx
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@ -114,6 +114,15 @@ def eth_arp_description(dw):
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]
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return EndpointDescription(layout, packetized=True)
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arp_table_request_layout = [
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("ip_address", 32)
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]
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arp_table_response_layout = [
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("failed", 1),
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("mac_address", 48)
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]
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def eth_ipv4_description(dw):
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layout = _layout_from_header(ipv4_header) + [
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("data", dw),
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@ -17,3 +17,93 @@ class LiteEthIPV4Packetizer(LiteEthPacketizer):
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eth_mac_description(8),
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ipv4_header,
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ipv4_header_len)
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class LiteEthIPTX(Module):
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def __init__(self, ip_address, arp_table):
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self.sink = sink = Sink(eth_ipv4_description(8))
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self.source = Source(eth_mac_description(8))
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###
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packetizer = LiteEthIPV4Packetizer()
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self.submodules += packetizer
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source = packetizer.sink
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("SEND_MAC_ADDRESS_REQUEST")
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)
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)
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fsm.act("SEND_MAC_ADDRESS_REQUEST",
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arp_table.request.stb.eq(1),
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arp_table.request.ip_address.eq(sink.destination_ip_address),
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If(arp_table.request.stb & arp_table.request.ack,
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NextState("WAIT_MAC_ADDRESS_RESPONSE")
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)
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)
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fsm.act("WAIT_MAC_ADDRESS_RESPONSE",
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# XXX add timeout
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If(arp_table.response.stb,
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# XXX manage failed
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NextState("SEND")
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)
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)
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fsm.act("SEND",
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Record.connect(packetizer.source, self.source),
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# XXX compute check sum
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# XXX add timeout
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If(arp_table.response.stb,
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# XXX manage failed
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NextState("SEND")
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)
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)
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class LiteEthIPRX(Module):
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def __init__(self, ip_address):
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self.sink = Sink(eth_mac_description(8))
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self.source = source = Source(eth_ipv4_description(8))
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###
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depacketizer = LiteEthIPV4Depacketizer()
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self.submodules += depacketizer
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self.comb += Record.connect(self.sink, depacketizer.sink)
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sink = depacketizer.source
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal()
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self.comb += valid.eq(1) # XXX FIXME
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fsm.act("CHECK",
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If(valid,
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NextState("PRESENT")
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).Else(
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NextState("DROP")
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)
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),
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fsm.act("PRESENT",
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Record.connect(sink, source),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("DROP",
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sink.ack.eq(1),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthIP(Module):
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def __init__(self, ip_address, arp_table):
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self.submodules.tx = LiteEthIPTX(ip_address, arp_table)
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self.submodules.rx = LiteEthIPRX(ip_address)
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self.sink, self.source = self.rx.sink, self.tx.source
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@ -15,3 +15,6 @@ mac_wishbone_tb:
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arp_tb:
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$(CMD) arp_tb.py
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ip_tb:
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$(CMD) ip_tb.py
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@ -0,0 +1,48 @@
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from liteeth.common import *
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from liteeth import LiteEthIPStack
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from liteeth.test.common import *
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from liteeth.test.model import phy, mac, arp
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ip_address = 0x12345678
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mac_address = 0x12345678abcd
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=True)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
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self.submodules.ip = LiteEthIPStack(self.phy_model, mac_address, ip_address)
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(100):
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yield
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#selfp.ip.sink.stb = 1
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#selfp.ip.sink.destination_ip_address = 0x12345678
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#selfp.ip.sink.source_ip_address = ip_address
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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